Characterization and Modeling of Native MOSFETs Down to 4.2 K

Zhang, Yuanke; Lu, Tengteng; Wang, Wenjie; Zhang, Yujing; Xu, Jun; Luo, Chao; Guo, Guo-Ping

doi:10.1109/ted.2021.3099775

Cited by 24 publications

(10 citation statements)

References 23 publications

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“…A zero-temperature coefficient (ZTC) point of −4.5 V can be obtained, as pointed out in figure 3(a). Notably, the ZTC point is inherent in different device technologies owing to the counterbalancing of different temperature-dependent effects contributing in opposite ways [1,27,28].…”

Section: Resultsmentioning

confidence: 99%

“…* Authors to whom any correspondence should be addressed. [1][2][3] and GaAs/InP [4,5] have been intensively studied as the readout/control circuits and low-noise amplifiers. Apart from these traditional devices, wide bandgap semiconductor GaNbased high-electron-mobility transistors (HEMTs) recently have emerged as a promising candidate for the cryo-systems thanks to their superior material and device properties [6][7][8].…”

Section: Introductionmentioning

confidence: 99%

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DC and low-frequency noise characteristics of GaN-based HEMTs under cryogenic temperatures

Zeng¹,

Zhang²,

Luo³

et al. 2022

J. Phys. D: Appl. Phys.

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In this work, the device characteristics of GaN-based high-electron-mobility transistors (HEMTs) were systematically investigated by the direct current (DC) and low-frequency noise (LFN) measurements within the temperature ranging from 300 K to 4.2 K. The temperature-dependent behavior of the on- and off-state electrical properties was statistically analyzed, highlighting an overall improved device performance under the cryogenic temperatures. In addition, the LFN of the device exhibited an evident behavior of 1/f noise from 10 Hz to 10 kHz in the measured temperature range and can be well described by the carrier number fluctuations with correlated mobility fluctuations (CNF/CMF) model down to 4.2 K. Based on this model, we further extracted and discussed the defect-related behavior in the devices under low-temperature environments. These experimental results provide insights into the device characteristics of GaN-based HEMTs under cryogenic environments, motivating further studies into the GaN-based cryo-devices and systems.

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Section: Resultsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

DC and low-frequency noise characteristics of GaN-based HEMTs under cryogenic temperatures

Zeng¹,

Zhang²,

Luo³

et al. 2022

J. Phys. D: Appl. Phys.

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“…DIBL is important because it causes drain current that depends on V d | | during saturation-mode operation and so can affect the operation of analog circuits. Interestingly, some studies have shown increases in DIBL at cryogenic temperatures [5][6][7][8][9] while others have not, [10][11][12][13][14] and this discrepancy has not been explained. In the present study, V t values were investigated at cryogenic temperatures with a focus on the impact of source and drain extension design on these values.…”

mentioning

confidence: 96%

Importance of source and drain extension design in cryogenic MOSFET operation: causes of unexpected threshold voltage increases

Inaba

Asai

Hattori

et al. 2022

Appl. Phys. Express

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Increased threshold voltages have been observed during linear-mode operation of short-channel bulk metal-oxide-semiconductor field-effect transistors (MOSFETs) employing shallow source and drain extension technology at cryogenic temperatures. These increases were suppressed during saturation-mode operation, which resulted in the increase of a threshold voltage mismatch between linear- and saturation-modes as if drain-induced barrier lowering occurred. Numerical simulations revealed that these increases originate from enhanced depletion in the extension region and subsequent increases in channel resistance at cryogenic temperatures. These data suggest that shallow extensions should be designed more carefully in the case of MOSFETs intended for cryogenic operation.

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“…[19][20][21][22] Forming self-aligned gates to obtain good control of gate lengths, is a key technique to improve VGAA FETs performance and integrated circuit (IC) manufacturability. [23][24][25] In our recent works, we have presented a new type of vertical sandwich gate-all-around FETs (VSAFETs), [26][27][28][29] which provide a method to form self-aligned gates and some new vertical devices with good electronic performance, such as N type VSAFETs, P type VSAFETs and Ferroelectric VSAFETs. In this work, we fabricated vertical gate-all around tunneling FETs (VSATFETs) with self-aligned highk metal gates and abrupt doping tunneling junctions for the first time.…”

mentioning

confidence: 99%

“…And by using in situ doping epitaxial technology, the abrupt doping tunneling junctions were performed in this work. The self-aligned gates were realized and the nanowire (NW) diameter/nanosheet (NS) thickness were defined precisely by selective qALE [26][27][28][29] process. The electrical characteristics had been measured and the influence of NS thickness/NW diameter on SS performance was studied and analyzed through TCAD simulation.…”

mentioning

confidence: 99%

First Demonstration of Vertical Sandwich GAA TFETs with Self-Aligned High-k Metal Gates and Abrupt Doping Tunneling Junctions

Zhang

Zhu

et al. 2023

ECS J. Solid State Sci. Technol.

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A new type of vertical sandwich gate-all around tunneling field-effect-transistors (GAA TFETs), called VSATFETs, was demonstrated firstly with a CMOS-compatible process. The VSATFETs with self-aligned high-κ metal gates (HKMG) and abrupt doping tunneling junctions were fabricated with the epitaxial of p+-Si/i-SiGe/n+-Si sandwich structure and an isotropic quasi-atomic layer-etch (qALE) process. VSATFETs have the advantage of excellent control of channel size, because its gate-length is mainly determined by the thickness of SiGe film grown by epitaxy, and the diameter of the nanowires (NWs) /thickness of nanosheets (NSs) is determined by the qALE etching of SiGe selective to Si. A NW VSATFET with a diameter of 18 nm was fabricated and exhibits excellent characteristics: SSmin = 61.64 mV/dec, Ion = 2.25 x 10-7 A/um (@Vgs-Vt = 0.45 V, Vd = 0.65 V), Ion/Ioff = 1.81 x 106, DIBL = 7.58 mV. The effect of interface traps on the device performance was analyzed by the calibrated model. It is found that the device performance can be improved by decreasing the thickness/diameter of NS/NW TFET.

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Characterization and Modeling of Native MOSFETs Down to 4.2 K

Cited by 24 publications

References 23 publications

DC and low-frequency noise characteristics of GaN-based HEMTs under cryogenic temperatures

DC and low-frequency noise characteristics of GaN-based HEMTs under cryogenic temperatures

Importance of source and drain extension design in cryogenic MOSFET operation: causes of unexpected threshold voltage increases

First Demonstration of Vertical Sandwich GAA TFETs with Self-Aligned High-k Metal Gates and Abrupt Doping Tunneling Junctions

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