Previous cryogenic electronics studies are mostly at 77K and 4.2K. Cryogenic characterization of a 0.18µm standard bulk CMOS technology (operating voltages: 1.8V and 5V) is presented in this paper. Several NMOS and PMOS devices with different width to length ratios (W/L) were extensively tested and characterized under various bias conditions at sub-kelvin temperature. In addition to devices dc characteristics, the kink effect and current overshoot phenomenon are observed and discussed at sub-kelvin temperature. Especially, the current overshoot phenomenon in PMOS devices at sub-kelvin temperature is shown for the first time. The transfer characteristics of MOSFET devices (1.8V W/L = 10µm/10µm) at sub-kelvin temperature are modeled using the simplified EKV model. This work facilitates the CMOS circuits design and the integration of CMOS circuits with silicon-based quantum chips at extremely low temperatures.
A novel power-efficient analog buffer at liquid helium temperature is proposed. The proposed circuit is based on an input stage consisting of two complementary differential pairs to achieve rail-to-rail level tracking. Results of simulation based on SMIC 0.18µm CMOS technology show the high driving capability and low quiescent power consumption at cryogenic temperature. Operating at single 1.4 V supply, the circuit could achieve a slew-rate of +51 V/µs and -93 V/µs for 10 pF capacitive load. The static power of the circuit is only 79µW.
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