A fast and low-cost sol-gel synthesis used to deposit a shell of TiO2 anatase onto an array of vertically aligned ZnO nanowires (NWs) is reported in this paper. The influence of the annealing atmosphere (air or N2) and of the NWs preannealing process, before TiO2 deposition, on both the physicochemical characteristics and photoelectrochemical (PEC) performance of the resulting heterostructure, was studied. The efficient application of the ZnO@TiO2 core-shells for the PEC water-splitting reaction, under simulated solar light illumination (AM 1.5G) solar light illumination in basic media, is here reported for the first time. This application has had a dual function: to enhance the photoactivity of pristine ZnO NWs and to increase the photodegradation stability, because of the protective role of the TiO2 shell. It was found that an air treatment induces a better charge separation and a lower carrier recombination, which in turn are responsible for an improvement in the PEC performance with respect to N2-treated core-shell materials. Finally, a photocurrent of 0.40 mA/cm(2) at 1.23 V versus RHE (2.2 times with respect to the pristine ZnO NWs) was obtained. This achievement can be regarded as a valuable result, considering similar nanostructured electrodes reported in the literature for this application.

With ever increasing demands on device patterning to achieve smaller critical dimensions, the need for precise, controllable atomic layer etching (ALE) is steadily increasing. In this work, a cyclical fluorocarbon/argon plasma is successfully used for patterning silicon oxide by ALE in a conventional inductively coupled plasma tool. The impact of plasma parameters and substrate electrode temperature on the etch performance is established. We achieve the self‐limiting behavior of the etch process by modulating the substrate temperature. We find that at an electrode temperature of −10°C, etching stops after complete removal of the modified surface layer as the residual fluorine from the reactor chamber is minimized. Lastly, we demonstrate the ability to achieve independent etching, which establishes the potential of the developed cyclic ALE process for small scale device patterning.

Single-electron devices operating at room temperature require sub-5 nm quantum dots having tunnel junctions of comparable dimensions. Further development in nanoelectronics depends on the capability to generate mesoscopic structures and interfacing these with complementary metal–oxide–semiconductor devices in a single system. The authors employ a combination of two novel methods of fabricating room temperature silicon single-electron transistors (SETs), Fowler–Nordheim scanning probe lithography (F-N SPL) with active cantilevers and cryogenic reactive ion etching followed by pattern-dependent oxidation. The F-N SPL employs a low energy electron exposure of 5–10 nm thick high-resolution molecular resist (Calixarene) resulting in single nanodigit lithographic performance [Rangelow et al., Proc. SPIE 7637, 76370V (2010)]. The followed step of pattern transfer into silicon becomes very challenging because of the extremely low resist thickness, which limits the etching depth. The authors developed a computer simulation code to simulate the reactive ion etching at cryogenic temperatures (−120 °C). In this article, the authors present the alliance of all these technologies used for the manufacturing of SETs capable to operate at room temperatures.

The next generation of hard disk drive technology for data storage densities beyond 5 Tb/in will require single-bit patterning of features with sub-10 nm dimensions by nanoimprint lithography. To address this challenge master templates are fabricated using pattern multiplication with atomic layer deposition (ALD). Sub-10 nm lithography requires a solid understanding of materials and their interactions. In this work we study two important oxide materials, silicon dioxide and titanium dioxide, as the pattern spacer and look at their interactions with carbon, chromium and silicon dioxide. We found that thermal titanium dioxide ALD allows for the conformal deposition of a spacer layer without damaging the carbon mandrel and eliminates the surface modification due to the reactivity of the metal-organic precursor. Finally, using self-assembled block copolymer lithography and thermal titanium dioxide spacer fabrication, we demonstrate pattern doubling with 7.5 nm half-pitch spacer features.

Nanoelectronics manufacturing requires an ongoing development of lithography and also encompasses some “unconventional” methods. In this context, the authors use field emission scanning probe lithography (FE-SPL) to generate nanoscaled electronic devices. For the generation of future novel quantum devices, such as single-electron transistors or plasmonic resonators, patterning of features in the sub-10 nm regime as well as a defined metallization is necessary. In terms of metallization, the authors take advantage of the well-known lift-off process for creating narrow gap junctions. Narrow gap electrodes have found wide approval in the formation of narrow gap junctions and can be employed for the investigation of the electrical properties of molecules. In the lift-off process presented here, two sacrificial layers (50 nm polymethylglutarimide and 10 nm calixarene) have been deposited and patterned by FE-SPL. Subsequently, the sample was treated with tetraethyl-ammonium hydroxide in order to ensure an undercut. Afterward, a layer of 10 nm thick Cr has been deposited on top and finally the sacrificial films have been removed, leaving behind only the chromium film deposited directly on the substrate. In this work, the authors will present the utilization of novel active cantilevers with diamond coated silicon tips for FE-SPL purposes in order to generate chromium metal features by lift-off for the generation of future quantum devices. In this context, they will present the integration of an ultrananocrystalline diamond (UNCD) layer deposited on the tip of an active silicon cantilever. Electron emission and FE-SPL capabilities of UNCD coated silicon tips are evaluated. The authors demonstrate a reliable fabrication scheme of sub-15 nm coplanar narrow gap metal electrodes.

In manufacturing, etch profiles play a significant role in device patterning. Here, the authors present a study of the evolution of etch profiles of nanopatterned silicon oxide using a chromium hard mask and a CHF 3 /Ar atomic layer etching in a conventional inductively coupled plasma tool. The authors show the effect of substrate electrode temperature, chamber pressure, and electrode forward power on the etch profile evolution of nanopatterned silicon oxide. Chamber pressure has an especially significant role, with lower pressure leading to lower etch rates and higher pattern fidelity. The authors also find that at higher electrode forward power, the physical component of etching increases and more anisotropic etching is achieved. By carefully tuning the process parameters, the authors are able to find the best conditions to achieve aspect-ratio independent etching and high fidelity patterning, with an average sidewall angle of 87°± 1.5°and undercut values as low as 3.7 ± 0.5% for five trench sizes ranging from 150 to 30 nm. Furthermore, they provide some guidelines to understand the impact of plasma parameters on plasma ion distribution and thus on the atomic layer etching process.

Free-electron lasers (FELs) currently represent a step forward on time-resolved investigations on any phase of matter through pump-probe methods involving FELs and laser beams. That class of experiments requires an accurate spatial and temporal superposition of pump and probe beams on the sample, which at present is still a critical procedure. More efficient approaches are demanded to quickly achieve the superposition and synchronization of the beams. Here, we present what we believe is a novel technique based on an integrated device allowing the simultaneous characterization and the fast spatial and temporal overlapping of the beams, reducing the alignment procedure from hours to minutes.

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