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With the recent advances in the field of nanotechnology, measurement and manipulation requirements at the nanoscale have become more stringent than ever before. In atomic force microscopy, high-speed performance alone is not sufficient without considerations of other aspects of the measurement task, such as the feature aspect ratio, required range, or acceptable probe-sample interaction forces. In this paper, the authors discuss these requirements and the research directions that provide the highest potential in meeting them. The authors elaborate on the efforts toward the downsizing of self-sensed and self-actuated probes as well as on upscaling by active cantilever arrays. The authors present the fabrication process of active probes along with the tip customizations carried out targeting specific application fields. As promising application in scope of nanofabrication, field emission scanning probe lithography is introduced. The authors further discuss their control and design approach. Here, microactuators, e.g., multilayer microcantilevers, and macroactuators, e.g., flexure scanners, are combined in order to simultaneously meet both the range and speed requirements of a new generation of scanning probe microscopes.

We describe a microcantilever calorimeter consisting of an array of ten cantilevers. Each single cantilever is capable of detecting heat energy with the resolution of 50 nW Hz (Ϫ0.5) . The device is based on a Si microcantilever coated with a 1 m thick layer of SiO 2 deposited with a 700 nm thick layer of aluminum which forms a resistive microheater. Heat fluxes are monitored by detecting the cantilever deflection ͑bending͒ due to the bimaterial structure of the cantilever ͑dissimilar thermal expansion properties of SiO 2 and Al͒. The resistive microheater serves for calibration of the heat flux and for temperature sensing. In our design a piezoresistive Wheatstone bridge detector is applied for measurements of the cantilever beam deflection. The cantilever displacement detection system enables investigations in ultrahigh vacuum and low temperature conditions. The microcantilevers are manufactured in a one-dimensional array having ten individual microcantilevers which is the first step in the fabrication of an infrared detector array with spatial resolution. The displacement sensitivity versus temperature change of the described sensor array as a function of temperature change is of about 2 nm/K and an estimated resolution limit of temperature detection is Ϸ10 Ϫ3 K at 300 K. In order to demonstrate the cantilever bending sensitivity we employ the piezoresistive cantilever array as a picogram microbalance.

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Dependence of the leakage current on the film quality in polycrystalline silicon thin-film transistors Empirical relationship between low-frequency drain current noise and grain-boundary potential barrier height in high-temperature-processed polycrystalline silicon thin-film transistorsThe off-state current in n-and p-channel polycrystalline silicon thin-film transistors ͑polysilicon TFTs͒ is investigated systematically by conduction measurements at various temperatures and low-frequency noise measurements at room temperature. It is demonstrated that the leakage current is controlled by the reverse biased drain junction. The main conduction mechanisms are due to thermal generation at low electric fields and Poole-Frenkel accompanied by thermionic filed emission at high electric fields. The leakage current is correlated with the traps present in the polysilicon bulk and at the gate oxide/polysilicon interface which are estimated from the on-state current activation energy data. Analysis of the leakage current noise spectral density confirms that deep levels with uniform energy distribution in the silicon band gap are the main factors in determining the leakage current. The density of deep levels determined from noise analysis is in agreement with the value obtained from conductance activation energy analysis. The substantially lower leakage current observed in the n-channel polysilicon TFT is explained by the development of positive fixed charges at the interface near the drain junction which suppress the electric field.

Scanning probe-based methods for surface modification and lithography are an emerging method of producing sub 20-nm features for nanoelectronic applications. In this study, we have demonstrated the nanoscale lithography based on patterning of 10 to 50-nm-thick calix[4]arene by electric-field-induced electrostatic scanning probe lithography. The features size control is obtained using electrostatic interactions and depends on the applied bias and speed of the AFM tip. The width of the obtained lines and dots varies from 10 to 60 nm depending on tip-sharpness, tip-substrate separation and tip-bias voltage.

Single-electron devices operating at room temperature require sub-5 nm quantum dots having tunnel junctions of comparable dimensions. Further development in nanoelectronics depends on the capability to generate mesoscopic structures and interfacing these with complementary metal–oxide–semiconductor devices in a single system. The authors employ a combination of two novel methods of fabricating room temperature silicon single-electron transistors (SETs), Fowler–Nordheim scanning probe lithography (F-N SPL) with active cantilevers and cryogenic reactive ion etching followed by pattern-dependent oxidation. The F-N SPL employs a low energy electron exposure of 5–10 nm thick high-resolution molecular resist (Calixarene) resulting in single nanodigit lithographic performance [Rangelow et al., Proc. SPIE 7637, 76370V (2010)]. The followed step of pattern transfer into silicon becomes very challenging because of the extremely low resist thickness, which limits the etching depth. The authors developed a computer simulation code to simulate the reactive ion etching at cryogenic temperatures (−120 °C). In this article, the authors present the alliance of all these technologies used for the manufacturing of SETs capable to operate at room temperatures.