Study of leakage current in n-channel and p-channel polycrystalline silicon thin-film transistors by conduction and low frequency noise measurements

Angelis, Constantinos T.; Dimitriadis, C. A.; Samaras, I.; Brini, J.; Kamarinos, G.; Gueorguiev, V.K.; Ivanov, Tzvetan

doi:10.1063/1.365720

Cited by 62 publications

(24 citation statements)

References 13 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Therefore, the suppression of the leakage current during the previously demonstrated stressing periods could be due to the passivation of these grain-boundary trap states. Reduction in transconductance has been previously described as a function of the density of strained-bond tail states [14]. Therefore, the results in Fig.…”

Section: B Device Stabilitymentioning

confidence: 77%

A Comparison of the Performance and Stability of ZnO-TFTs With Silicon Dioxide and Nitride as Gate Insulators

Cross

Souza

Deane

et al. 2008

IEEE Trans. Electron Devices

101

View full text Add to dashboard Cite

Abstract-The performance and stability of thin-film transistors with zinc oxide as the channel layer are investigated using gate bias stress. It is found that the effective channel mobility, ON/OFF ratio, and subthreshold slope of the devices that incorporate SiN are superior to those with SiO 2 as the dielectric. The application of positive and negative stress results in the device transfer characteristics shifting in positive and negative directions, respectively. The devices also demonstrate a logarithmic time-dependent threshold voltage shift suggestive of charge trapping within the band gap and the band tails responsible for the deterioration of device parameters. It is postulated that this device instability is partly a consequence of the lattice mismatch at the channel/insulator interface. All stressed devices recover to near-original characteristics after a short period at room temperature without the need for any thermal or bias annealing.

show abstract

Section: B Device Stabilitymentioning

confidence: 77%

A Comparison of the Performance and Stability of ZnO-TFTs With Silicon Dioxide and Nitride as Gate Insulators

Cross

Souza

Deane

et al. 2008

IEEE Trans. Electron Devices

101

View full text Add to dashboard Cite

show abstract

“…The reasonable explanation is that the small grain poly-Si in the LDD region of high laser energy-activated LDD TFTs offers lots of trap states and thus enhances the thermionic field-emission in the LDD region. 8 Therefore, a high laser energy-activated LDD TFT does not reveal a leakage current lower than that of the low laser energyactivated LDD TFT, even with higher series resistance in the LDD region. On the other hand, the I D -V G characteristics at V DS ϭ 0.1 V are also measured to realize the field-effect mobilities.…”

Section: Resultsmentioning

confidence: 98%

Effects of Excimer Laser Dopant Activation on Low Temperature Polysilicon Thin-Film Transistors with Lightly Doped Drains

Tseng

Lin

Chang

et al. 2001

Electrochem. Solid-State Lett.

View full text Add to dashboard Cite

Excimer laser annealing has been utilized to manufacture low temperature polycrystalline silicon thin-film transistors with lightly doped drain ͑LDD͒ structures. The excimer laser annealing can effectively reduce the thermal budget of source/drain dopant activation, namely, without substrate heating. With the advantages of LDD structure, high performance device characteristics with a low ''off'' state current of 4.38 ϫ 10 Ϫ12 A/m, high on/off current ratio of 1.6 ϫ 10 7 , and good field-effect mobility of 268 cm 2 /V s, can be achieved simultaneously.One of the important device evaluation factors for lowtemperature poly-Si thin-film transistors ͑LTPS TFTs͒ is the current leakage. 1 The leakage current of poly-Si TFTs is correlated with current conduction through the defects at the grain boundaries and gate oxide/poly-Si interface at the high drain electric field. Therefore, lateral electric field reduction of drain junction is important to reduce the leakage current in LTPS TFTs. Although drain engineering using offset-gate structure TFTs, 2 lightly doped drain ͑LDD͒ TFTs, 3 and field-induced-drain ͑FID͒ TFTs 4 have been reported to reduce off-state leakage current, and these investigations employed conventional furnace to activate implanted dopants with high thermal budget which is too high for advanced plastic substrate. In contrast, excimer laser annealing ͑ELA͒ recently has attracted much attention because of the advantages of low process temperature even at room temperature process. Thus, ELA process has high potential for high resolution display on glass or even plastic substrate applications. 5 In this paper, ELA is therefore proposed to fabricate the LTPS TFTs with LDD structures. We have utilized a KrF excimer laser to crystallize amorphous Si and activate the dopants in the source/drain ͑s/d͒ and LDD regions of the TFTs. High field-effect mobility, low leakage current, and high on/off current ratio can be attained simultaneously. Figure 1 shows the main process sequences of the LDD poly-Si TFTs and the process steps are described as follows. 1000 Å thick amorphous silicon was first deposited by low pressure chemical vapor deposition ͑LPCVD͒ at 550°C on a Si substrate with 0.5 m thick thermal oxide. This is the highest thermal cycle used in this work and can be reduced using plasma enhanced CVD ͑PECVD͒. A scanning-type KrF excimer laser with Gaussian beam shape of 1.8 mm width and 23 mm length was used to crystallize the amorphous Si film. The condition of excimer laser crystallization is set at the energy density of 320 mJ/cm 2 and 99% overlapping of the beam width as well as 10 Hz repetition rate at 400°C substrate temperature. This crystallization resulted in the poly-Si film with an average grain size of 8000 Å. After the definition of active islands, 1000 Å thick Si dioxide film was deposited by PECVD at 300°C and used as the gate dielectric. Then 5000 Å thick Al film was thermally evaporated and used as the gate metal. The Al and the gate oxide films were patterned sequentially as the gate electrod...

show abstract

“…In general, the mechanisms of the carrier generation are divided into pure field emission, thermionic field emission, and Pool-Frenkel emission. 16 The pure field emission mechanism could be eliminated because the leakage current in our study was strongly dependent on the temperature. Therefore, the Pool-Frenkel effect and thermal field effect are the most likely generation mechanism.…”

Section: Methodsmentioning

confidence: 98%

Analysis of Anomalous Capacitance Induced by TAGIDL in p-Channel LTPS TFTs

Lin¹,

Chen²,

Chang

et al. 2010

J. Electrochem. Soc.

View full text Add to dashboard Cite

In this work, a mechanism of anomalous capacitance in p-channel low temperature polycrystalline silicon thin film transistors ͑LTPS TFTs͒ was investigated. In general, the effective capacitance of the LTPS TFTs was only dependent with the overlap area between the gate and source/drain under the off-state. However, the experimental results reveal that the off-state capacitance was increased with decreasing measurement frequency and/or with increasing measurement temperature. By fitting the curve of the drain current vs electric field under off-state region, it was verified that the trap-assisted gate-induced drain leakage ͑TAGIDL͒ consists of the Pool-Frenkel emission and thermal field emission. In addition, the charge density calculated from the C gsd -V g measurement also has the same dependence with electric field. This result demonstrates that the anomalous capacitance is mainly due to the TAGIDL. To suppress the anomalous capacitance, a band-to-band hot electron stress was utilized to reduce the vertical electric field between the gate and the drain. The electric field simulation was also performed by TCAD software.Low temperature polycrystalline silicon thin film transistors ͑LTPS TFTs͒ have been widely investigated for flat panel applications, such as for active matrix liquid crystal displays and active matrix organic light emitting diode displays 1,2 because the electron mobility of LTPS TFTs is higher than that of conventional amorphous silicon ͑a-Si͒ TFTs. Because the maximum process temperature is lower than 600°C, LPTS TFTs can be fabricated on cheap glass. This feature allows the fabrication of a pixel array and peripheral circuits on the same glass substrate. Consequently, this technology becomes more suitable to integrate both the pixel array and peripheral circuits on system-on-panel display, 3,4 and the LTPS TFTs are designed using complementary metal oxide semiconductor inverters. However, in previous papers, the results indicated that large leakage current is an important problem in p-channel LTPS TFTs. 5 The dominant mechanisms of the leakage current in LTPS TFTs have been widely studied, 6,7 and most of that have been focused on the analyses of current-voltage ͑I-V͒ transfer characteristics. However, it is rather difficult to investigate the relationship between capacitance-voltage ͑C-V͒ transfer characteristics and leakage current. Besides, most studies of C-V transfer characteristics in LTPS TFTs are mainly reported to monitor the electrical stress induced degradation in the transition region. 8,9 However, the leakage current dependent C-V in the off-state region was not investigated carefully. The purpose of this work is to investigate the relationship between the leakage current and C-V transfer characteristics in LTPS TFTs. The trap-assisted gate-induced drain leakage ͑TAGIDL͒ induced capacitance was observed and verified. In addition, we used an electrical stress to suppress the TAGIDL-induced capacitance and used the simulator TCAD to demonstrate the mechanism. ExperimentalIn this work,...

show abstract

Study of leakage current in n-channel and p-channel polycrystalline silicon thin-film transistors by conduction and low frequency noise measurements

Cited by 62 publications

References 13 publications

A Comparison of the Performance and Stability of ZnO-TFTs With Silicon Dioxide and Nitride as Gate Insulators

A Comparison of the Performance and Stability of ZnO-TFTs With Silicon Dioxide and Nitride as Gate Insulators

Effects of Excimer Laser Dopant Activation on Low Temperature Polysilicon Thin-Film Transistors with Lightly Doped Drains

Analysis of Anomalous Capacitance Induced by TAGIDL in p-Channel LTPS TFTs

Contact Info

Product

Resources

About