Gallium nitride (GaN) is a compound semiconductor that has tremendous potential to facilitate economic growth in a semiconductor industry that is silicon-based and currently faced with diminishing returns of performance versus cost of investment. At a material level, its high electric field strength and electron mobility have already shown tremendous potential for high frequency communications and photonic applications. Advances in growth on commercially viable large area substrates are now at the point where power conversion applications of GaN are at the cusp of commercialisation. The future for building on the work described here in ways driven by specific challenges emerging from entirely new markets and applications is very exciting. This collection of GaN technology developments is therefore not itself a road map but a valuable collection of global state-of-the-art GaN research that will inform the next phase of the technology as market driven requirements evolve. First generation production devices are igniting large new markets and applications that can only be achieved using the advantages of higher speed, low specific resistivity and low saturation switching transistors. Major investments are being made by industrial companies in a wide variety of markets exploring the use of the technology in new circuit topologies, packaging solutions and system architectures that are required to achieve and optimise the system advantages offered by GaN transistors. It is this momentum that will drive priorities for the next stages of device research gathered here.

The stability of thin film transistors incorporating sputtered ZnO as the channel layer is investigated under gate bias stress. Positive stress results in a positive shift of the transfer characteristics, while negative stress results in a negative shift. Low bias stress has no effect on the subthreshold characteristics. This instability is believed to be a consequence of charge trapping at/near the channel/insulator interface. Higher biases and longer stress times cause degradation of the subthreshold slope, which is thought to arise as a consequence of defect state creation within the ZnO channel material. After all stress measurements, the devices recover their original characteristics at room temperature without any annealing.

The effects of gold deposition on monolayer graphene (MG) epitaxied on SiC (0001) substrate are examined via scanning tunneling microscopy and scanning tunneling spectroscopy (STS). Two types of surfaces with distinctive topography are demonstrated: (i) intercalated gold clusters having no interaction with graphene and (ii) 13×13-G reconstruction attributed to a Moiré pattern arising from the intercalation of 1 ML of gold between a MG and the underlying SiC substrate. This surface also displays a 23×23R30-Au (111) surface reconstruction interpreted as surface corrugation. The STS curve shows a possible hole-doping effect in the latter case.

The growth of large-area, patterned and oriented ZnO nanowires on silicon using a low temperature silicon-CMOS compatible process is demonstrated. Nanowire synthesis takes place using a thin nucleation layer of ZnO deposited by radiofrequency magnetron sputtering, followed by a hydrothermal growth step. No metal catalysts are used in the growth process. The ZnO nanowires have a wurtzite structure, grow along the c-axis direction and are distributed on the silicon substrate according to the pre-patterned nucleation layer. Room temperature PL measurements of the as-grown nanowires exhibit strong yellow-red emission under 325 nm excitation that is replaced by ultraviolet emission after annealing. This method can be used to integrate patterned 1D nanostructures in optoelectronic and sensing applications on standard silicon CMOS wafers.

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