We report the development of gallium arsenide (GaAs) films grown on V-groove patterned (001) silicon (Si) by metalorganic chemical vapor deposition. This technique can provide an advanced virtual substrate platform for photonic integrated circuits on Si. A low defect density of 9.1 × 106 cm−2 was achieved with the aspect ratio trapping capability of the V-grooved Si and dislocation filtering approaches including thermal cycle annealing and dislocation filter layers. The efficiencies of these dislocation reduction methods are quantified by statistical electron channeling contrast imaging characterization. Meanwhile, different sets of dislocation filtering layers are evaluated and optimized. To further demonstrate the suitability of GaAs on the V-grooved Si technique for Si-based photonic devices, especially for the appealing 1.3 μm quantum dot (QD) lasers, a 7-layer indium arsenide QD structure was grown on both GaAs-on-V-grooved Si and native GaAs substrates. The same photoluminescence intensity and full-width at half-maximum values were observed for both structures. The optimization methodology in this work therefore offers a feasible approach to realize high quality III–V materials on Si for large-scale integration.

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We report on the successful integration of multiple atomically thin horizontal heterojunctions (HJs) epitaxially grown via metal organic chemical vapor deposition inside a confined template of dielectric material. InAs, GaAs, and InGaAs layers were included in laterally grown InP structures and characterized to show abrupt interfaces and crystalline material. The orientation of the templates and the substrate is chosen so that a flat vertical facet appears at the growth front allowing for the HJs to be horizontal, unlike typical planar epitaxy. This enables the design of recently proposed novel electronic HJ devices like triple-HJ tunnel field-effect transistors.

An indium phosphide (InP)-based photonic integrated circuit (PIC) transmitter for free space optical communications was demonstrated. The transmitter consists of a sampled grating distributed Bragg reflector (SGDBR) laser, a high-speed semiconductor optical amplifier (SOA), a Mach-Zehnder modulator, and a high-power output booster SOA. The SGDBR laser tunes from 1521 nm to 1565 nm with >45 dB side mode suppression ratio. The InP PIC was also incorporated into a free space optical link to demonstrate the potential for low cost, size, weight and power. Error-free operation was achieved at 3 Gbps for an equivalent link length of 180 m (up to 300 m with forward error correction).

Selectively growing epitaxial material in confined dielectric structures has been explored recently as a pathway to integrate highly mismatched materials on silicon substrates. This approach involves the fabrication of a channel-like structure of dielectric material that from the growth atmosphere reaches down to a small exposed area of the substrate where subsequent growth via metal organic chemical vapor deposition (MOCVD) initiates. The technique, referred to as template assisted selective epitaxy, can also enable the development of novel nanoscale photonic and electronic device structures because of its ability to allow epitaxy to progress in a direction, final size, and aspect ratio defined by the dielectric template, and allows integration of horizontal heterojunction inside the channel. To date, most confined epitaxy work has been detailed on silicon. Due to the reduced chemical and thermal stability of InP compared to Si, additional steps for surface preparation are required. In this work, two different fabrication routes are described on InP substrates: one involving amorphous silicon as a sacrificial layer and deposited SiO2 as top oxide, while the other involves spin coated photoresist and hydrogen-silsesquioxane sourced SiOx. Both routes, leading to similar template structures, are demonstrated and discussed. Homoepitaxy of InP in both types of templates and the integration of an InAs horizontal heterojunction are demonstrated via MOCVD. An increase in growth rate with decreasing template length, increasing template width, and decreasing pattern density is observed.

We report on the use of InGaAsP strain-compensated superlattices (SC-SLs) as a technique to reduce the defect density of Indium Phosphide (InP) grown on silicon (InP-on-Si) by Metal Organic Chemical Vapor Deposition (MOCVD). Initially, a 2 μm thick gallium arsenide (GaAs) layer was grown with very high uniformity on exact oriented (001) 300 mm Si wafers; which had been patterned in 90 nm V-grooved trenches separated by silicon dioxide (SiO2) stripes and oriented along the [110] direction. Undercut at the Si/SiO2 interface was used to reduce the propagation of defects into the III–V layers. Following wafer dicing; 2.6 μm of indium phosphide (InP) was grown on such GaAs-on-Si templates. InGaAsP SC-SLs and thermal annealing were used to achieve a high-quality and smooth InP pseudo-substrate with a reduced defect density. Both the GaAs-on-Si and the subsequently grown InP layers were characterized using a variety of techniques including X-ray diffraction (XRD); atomic force microscopy (AFM); transmission electron microscopy (TEM); and electron channeling contrast imaging (ECCI); which indicate high-quality of the epitaxial films. The threading dislocation density and RMS surface roughness of the final InP layer were 5 × 108/cm2 and 1.2 nm; respectively and 7.8 × 107/cm2 and 10.8 nm for the GaAs-on-Si layer.