Horizontal Heterojunction Integration via Template-Assisted Selective Epitaxy

Brunelli, Simone Tommaso Šuran; Goswami, Aranya; Markman, Brian; Tseng, Hsin-Ying; Rodwell, M.J.W.; Palmstrøm, C. J.; Klamkin, Jonathan

doi:10.1021/acs.cgd.9b00843

Cited by 11 publications

(10 citation statements)

References 27 publications

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“…Further studies to finetune the epitaxial processes are ongoing. We note that using a similar geometry on a InP substrate the growth of sharp and vertical quantum wells was demonstrated [31,32]. Fig.…”

Section: Resultsmentioning

confidence: 82%

Waveguide coupled III-V photodiodes monolithically integrated on Si

et al. 2022

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The seamless integration of III-V nanostructures on silicon is a long-standing goal and an important step towards integrated optical links. In the present work, we demonstrate scaled and waveguide coupled III-V photodiodes monolithically integrated on Si, implemented as InP/In0.5Ga0.5As/InP p-i-n heterostructures. The waveguide coupled devices show a dark current down to 0.048 A/cm2 at −1 V and a responsivity up to 0.2 A/W at −2 V. Using grating couplers centered around 1320 nm, we demonstrate high-speed detection with a cutoff frequency f3dB exceeding 70 GHz and data reception at 50 GBd with OOK and 4PAM. When operated in forward bias as a light emitting diode, the devices emit light centered at 1550 nm. Furthermore, we also investigate the self-heating of the devices using scanning thermal microscopy and find a temperature increase of only ~15 K during the device operation as emitter, in accordance with thermal simulation results.

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Section: Resultsmentioning

confidence: 82%

Waveguide coupled III-V photodiodes monolithically integrated on Si

et al. 2022

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“…Advantages of using gold catalyst free nanowire growth are: 1) removing the catalyst from the process, making it more complementary metal-oxide semiconductor compatible by removing risk of gold-related deep level doping of silicon, [59] and 2) the possibility of making abrupt junction transitions along the nanowire. [60] A disadvantage is the atomic layer defects often seen in gold-free nanowire growth, such as twin planes, stacking faults, or polytypism, [53] which potentially could affect performance for some devices. However, a study by Zhuang et al using indium droplet assisted growth showed how a 2-4 at% inclusion of antimony (Sb) in indium arsenide (InAs) nanowires, generated quasi-pure WZ structure, whereas a 10 at% inclusion generated quasi-pure ZB structure.…”

Section: Inas Nanowires From Directed Self-assemblymentioning

confidence: 99%

Directed Self‐Assembly for Dense Vertical III–V Nanowires on Si and Implications for Gate All‐Around Deposition

Löfstrand

Jam

Svensson

et al. 2022

Adv Elect Materials

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Fabrication of next generation transistors calls for new technological requirements, such as reduced size and increased density of structures. Development of cost‐effective processing techniques to fabricate small‐pitch vertical III–V nanowires over large areas will be an important step toward realizing dense gate all‐around transistors, having high electron mobility, and low power consumption. It is demonstrated here, how arrays of III–V nanowires with a controllable number of rows, ranging from one single row up to bands of 500 nm, can be processed by directed self‐assembly (DSA) of block copolymer (BCP). Furthermore, it is shown that the DSA‐orientation with respect to the substrate's crystal direction affects the nanowire facet configuration, and thereby the nanowire spacing and gate all‐around deposition possibilities. A high χ poly(styrene)‐block‐poly(4‐vinylpyridine) BCP pattern directed by electron beam lithography‐defined guiding lines is transferred into silicon nitride. The silicon nitride is then used as a selective area metal‐organic vapor phase epitaxy mask atop an indium arsenide (InAs) buffer layer on a silicon platform to grow vertical InAs nanowires at 44–60 nm row pitch. Finally, deposition of high‐κ oxide and titanium nitride at this high pattern density is demonstrated, to further illustrate the considerations needed for next generation transistors.

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“…It can represent a single solution for the integration of all major photonic components [12,13] such as, photodetectors [12,14], emitters [15,16], modulators, and waveguides. While TASE structures grown with a single growth facet have been reported on III-V substrates [17,18], a multifaceted end surface is the most common situation for structures grown on Si [9,11,[19][20][21]. This is not inherently an issue for binary III-V microstructures.…”

Section: Introductionmentioning

confidence: 99%