Strain-Compensated InGaAsP Superlattices for Defect Reduction of InP Grown on Exact-Oriented (001) Patterned Si Substrates by Metal Organic Chemical Vapor Deposition

Abstract

We report on the use of InGaAsP strain-compensated superlattices (SC-SLs) as a technique to reduce the defect density of Indium Phosphide (InP) grown on silicon (InP-on-Si) by Metal Organic Chemical Vapor Deposition (MOCVD). Initially, a 2 μm thick gallium arsenide (GaAs) layer was grown with very high uniformity on exact oriented (001) 300 mm Si wafers; which had been patterned in 90 nm V-grooved trenches separated by silicon dioxide (SiO2) stripes and oriented along the [110] direction. Undercut at the Si/SiO2 interface was used to reduce the propagation of defects into the III–V layers. Following wafer dicing; 2.6 μm of indium phosphide (InP) was grown on such GaAs-on-Si templates. InGaAsP SC-SLs and thermal annealing were used to achieve a high-quality and smooth InP pseudo-substrate with a reduced defect density. Both the GaAs-on-Si and the subsequently grown InP layers were characterized using a variety of techniques including X-ray diffraction (XRD); atomic force microscopy (AFM); transmission electron microscopy (TEM); and electron channeling contrast imaging (ECCI); which indicate high-quality of the epitaxial films. The threading dislocation density and RMS surface roughness of the final InP layer were 5 × 108/cm2 and 1.2 nm; respectively and 7.8 × 107/cm2 and 10.8 nm for the GaAs-on-Si layer.

Heteroepitaxial Growth of III-V Semiconductors on Silicon

“…In Figure 15d, it was shown that the employment of three sets of In 0.18 Ga 0.82 As/GaAs SLSs DFLs effectively blocked and annihilated the TDs. In the InP/Si platform, the DFLs based on InGaAs/InP, In(Ga)AsP/InP, (In)GaP/InP, and so on [149,170,[225][226][227][228][229][230] have been also commonly adopted. For instance, Shi et al [149] reported the effect of In0.73Ga0.27As/InP SLSs DFLs on the reduction of TDD in InP grown on on-axis (001) Si.…”

“…For example, the TDD of InP-based materials remains on the order of 10 8 cm −2 , while, in GaAs-based materials, the order of 10 6 cm −2 can be achieved. The reason for the discrepancy is not clearly understood, but it is believed to be due to the phase separation in the SLSs and/or the high density of dislocations arising from larger lattice mismatch in InP/Si than In the InP/Si platform, the DFLs based on InGaAs/InP, In(Ga)AsP/InP, (In)GaP/InP, and so on [149,170,[225][226][227][228][229][230] have been also commonly adopted. For instance, Shi et al [149] reported the effect of In 0.73 Ga 0.27 As/InP SLSs DFLs on the reduction of TDD in InP grown on on-axis (001) Si.…”

Metamorphic Integration of GaInAsSb Material on GaAs Substrates for Light Emitting Device Applications

“…The TDs, which can act as non-recombination centers and electrical channels, can seriously deteriorate the material quality and device performances [7,8]. Various epitaxial methods have been investigated for the suppression of TDs during the growth of materials with large lattice mismatch, which include graded buffer layers [9], dislocation filtering layers [10], interlayer structures [11] and strain compensation [12]. However, little has been reported on the integration of GaInAsSb based devices on GaAs substrates.…”

Influence of Growth Temperature of the Nucleation Layer on the Growth of InP on Si (001)

“…Based on the existing technologies, flip-chip bonding and micro-transfer printing are easier to implement, but the two approaches are also confronted by the chip and transfer-layer size, interconnect size and losses, and the complexity of manufacture. Therefore, direct epitaxial growth is considered as the most promising approach in the future [12,13]. However, it still faces enormous challenges owing to the large lattice mismatch, thermal mismatch, and antiphase boundaries caused by crystal polarity difference.…”