MOCVD grown low dislocation density GaAs-on-V-groove patterned (001) Si for 1.3 μ m quantum dot laser applications

Abstract

We report the development of gallium arsenide (GaAs) films grown on V-groove patterned (001) silicon (Si) by metalorganic chemical vapor deposition. This technique can provide an advanced virtual substrate platform for photonic integrated circuits on Si. A low defect density of 9.1 × 106 cm−2 was achieved with the aspect ratio trapping capability of the V-grooved Si and dislocation filtering approaches including thermal cycle annealing and dislocation filter layers. The efficiencies of these dislocation reduction methods are quantified by statistical electron channeling contrast imaging characterization. Meanwhile, different sets of dislocation filtering layers are evaluated and optimized. To further demonstrate the suitability of GaAs on the V-grooved Si technique for Si-based photonic devices, especially for the appealing 1.3 μm quantum dot (QD) lasers, a 7-layer indium arsenide QD structure was grown on both GaAs-on-V-grooved Si and native GaAs substrates. The same photoluminescence intensity and full-width at half-maximum values were observed for both structures. The optimization methodology in this work therefore offers a feasible approach to realize high quality III–V materials on Si for large-scale integration.

Strained CdZnTe/CdTe Superlattices As Threading Dislocation Filters in Lattice Mismatched MBE Growth of CdTe on GaSb

“…In 0.18 Ga 0.82 As/GaAs (10 nm/10 nm) SLSs, 18,19 which are comparable to the $ 70% dislocation filtering efficiency found in this study for the II-VI CdZnTe/CdTe superlattice DFLs.…”

“…Figure 5a also includes the evolution of TD density within GaAs buffer layers grown on Si after incorporating strained III-V GaInAs/GaAs superlattice DFLs as observed by TEM. 18,19 Although the absolute values of TD density are not directly comparable, the dislocation filtering efficiency can be deduced to be 80% for the two-sets-of-ten-period In 0.16 Ga 0.84 As/GaAs (12 nm/ 12 nm) SLSs, and $ 75% for the four-sets-of-fiveperiod…”

“…Over 30 years of effort, this concept has been demonstrated successfully in the growth of III-V semiconductors on lattice mismatched substrates, in which the dislocation density was reduced from $ 10 9 cm À2 to $ 10 5 cm À2 for GaAs buffer layers grown on Si by incorporating InGaAs/GaAs strained-layer superlattices, 17 leading to high-performance InAs/GaAs quantum dot lasers. 18,19 Despite the five orders of magnitude decrease in dislocation density that has been claimed for a 13-lm-thick CZT buffer on GaAs(001) due to the insertion of a dislocation filtering layers (DFL) consisting of 15 periods of 250-nm-thick Cd 0.91 Zn 0.09 Te/CdTe, 20 there have been few further studies reported in the open literature, and the related superlattice-based DFL technique has yet to become commercially viable. [21][22][23][24] In this work, multiple sets of CdZnTe/CdTe superlattice-based layers have been studied as dislocation filters for reducing the TDs and thus improving the material quality of CdTe buffers grown on GaSb (211)B substrates.…”

Inversion Boundary Annihilation in GaAs Monolithically Grown on On‐Axis Silicon (001)

“…[16,17] However, this strategy is incompatible with CMOS technology, which strictly requires nominal on-axis Si (001) substrates. [18] Until now, great efforts have been made to develop epitaxial growth techniques for IB-free III-V materials on on-axis Si (001) substrates including the implementation of V-groove patterned Si substrate, [19][20][21] template-assisted selective epitaxy (TASE), [22,23] III-V nano-ridge engineering [24,25] and high temperature annealing of Si substrate under hydrogen ambient environment by using metal organic chemical vapor deposition (MOCVD) systems. [26][27][28] With the aid of high temperature and high-pressure hydrogen, the epitaxial growth of IB-free GaP and GaAs on D-dominated Si has achieved great success.…”

State of the Art and Future Perspectives in Advanced CMOS Technology

“…Integrated with other epitaxial technologies, GaAs, InP, and even quantum wells on Si, Ge, SOI, GOI substrates are demonstrated in [ 328 , 329 , 330 , 331 , 332 ]. As an example, Shi [ 333 ] made use of InGaAs/GaAs SLs and thermal cycling annealing to achieve high-quality InAs/InGaAs/GaAs quantum dots (QDs) structure on V-grooved patterned Si in Figure 47 b,c. The surface roughness reported in root mean square was 1.46 nm while threading dislocation density reached 9.1 × 10 6 cm −2 .…”