In oxide chemical-mechanical polishing (CMP) processes, layout pattern dependent variation in the interlevel dielectric (ILD) thickness can reduce yield and impact circuit performance. Metal-fill patterning practices have emerged as a technique for substantially reducing layout pattern dependent ILD thickness variation. We present a generalizable methodology for selecting an optimal metal-fill patterning practice with the goal of satisfying a given dielectric thickness variation specification while minimizing the added interconnect capacitance associated with metal-fill patterning. Data from two industrialbased experiments demonstrate the beneficial impact of metalfill on dielectric thickness variation, a 20% improvement in uniformity in one case and a 60% improvement in the other case, and illustrate that pattern density is the key mechanism involved. The pros and cons of two different metal-fill patterning practices-grounded versus floating metal-are explored. Criteria for minimizing the effect of floating or grounded metal-fill patterns on delay or crosstalk parameters are also developed based on canonical metal-fill structures. Finally, this methodology is illustrated using a case study which demonstrates an 82% reduction in ILD thickness variation. Index Terms-Chemical-mechanical polishing (CMP), design for manufacturing, metal-fill, within-die variation. I. INTRODUCTION I N recent years, chemical-mechanical polishing (CMP) has emerged as the primary technique for planarizing interlayer dielectrics [1], [2]. Although CMP is very effective at reducing the as-deposited step height and achieves a measure of global planarization not possible with either spin-on or resist etchback Manuscript

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GaAs MESFET-based switches suffer from high insertion losses. As an alternative, GaAs RF MEMS have shown great promise due to high isolation, low insertion losses, and wide bandwidths. Some factors constraining the fabrication have been suitable planarization techniques, quality of metallisation, stress in the beams, and elimination of stiction of beams to the central signal electrode. Quality of metallisation makes pulse reversal plating technique viable for production compared to DC plating. Coplanar waveguide pads, anchors, and beams are formed using this process. This paper discusses the optimization of pulse reversal electrodeposition process to fabricate different stages of RF MEMS switches.

In this paper a triple level metal interconnect process for a coqimercially available high density, high performance 0.6 tm/5V CMOS technology is described. Polyates of 0.6 p.m (Leff 0.45 p.m) were fabricated and then planarized by BPSG reflow and resist etch back. Blanket W and etch back was used to fill high aspect ratio contacts and vias with TIN as the nucleation barrier. Low temperature RTA was performed after TiTFiN deposition, and RF etch was performed for contacts and vias respectively, prior to TiTfiN depositing, to achieve reliable contacts and via resistance. Stable contacts/via resistance down to 0.7 m with goodjunction integrity/stackability and negative metal enclosure has been demonstrated and been physically characterized by HTEM. TiN/AL-Cu/TiN was used for M1/M2/M3 interconnection and TEOS/ resist etch back /TEOS refill was used for lID 1 and ILD2. A TEOS/nitride sandwich was used for final passivation. A satisfactory yield has been achieved on 2.9 cm2 die size with 0.6 million usable gates.

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