In oxide chemical-mechanical polishing (CMP) processes, layout pattern dependent variation in the interlevel dielectric (ILD) thickness can reduce yield and impact circuit performance. Metal-fill patterning practices have emerged as a technique for substantially reducing layout pattern dependent ILD thickness variation. We present a generalizable methodology for selecting an optimal metal-fill patterning practice with the goal of satisfying a given dielectric thickness variation specification while minimizing the added interconnect capacitance associated with metal-fill patterning. Data from two industrialbased experiments demonstrate the beneficial impact of metalfill on dielectric thickness variation, a 20% improvement in uniformity in one case and a 60% improvement in the other case, and illustrate that pattern density is the key mechanism involved. The pros and cons of two different metal-fill patterning practices-grounded versus floating metal-are explored. Criteria for minimizing the effect of floating or grounded metal-fill patterns on delay or crosstalk parameters are also developed based on canonical metal-fill structures. Finally, this methodology is illustrated using a case study which demonstrates an 82% reduction in ILD thickness variation. Index Terms-Chemical-mechanical polishing (CMP), design for manufacturing, metal-fill, within-die variation. I. INTRODUCTION I N recent years, chemical-mechanical polishing (CMP) has emerged as the primary technique for planarizing interlayer dielectrics [1], [2]. Although CMP is very effective at reducing the as-deposited step height and achieves a measure of global planarization not possible with either spin-on or resist etchback Manuscript
Based on Rent's rule, a well-established empirical relationship, a rigorous derivation of the interconnect fanout distribution for random logic networks is performed. Through comparison with actual product data, it is shown that the model successfully predicts the fan-out distribution of a random logic network. Using the closed form expression for the fan-out distribution, its application to predict the global level netlist information in a system-on-achip is presented.
In this paper the overall pin versus gate relationship of a heterogeneous system is derived based on the Rent's rule parameters of each megacell in the system. It is shown that, a composite Rent's rule successfully describes a heterogeneous collection of megacells.
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