Impact of interconnect pattern density information on a 90 nm technology ASIC design flow

Zarkesh-Ha, Payman; Lakshminarayanan, S.; Doniger, Ken; Loh, W.; Wright, P.J.

doi:10.1109/isqed.2003.1194767

Cited by 15 publications

(15 citation statements)

References 9 publications

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“…The interconnect pattern density is initially limited by the design rules within 20% -80% metal fill [14]. A statistical analysis of the pattern density of a real chip showed that, typically, the maximum pattern density in actual metal layers does not exceed 60% [15]. Thus metal fill factors f in the range 0.3 -0.6 is considered.…”

Section: Methodsmentioning

confidence: 99%

Empirical Mixing Model for the Electromagnetic Compatibility Analysis of On-Chip Interconnects

Holik¹

2012

Dielectric Material

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Section: Methodsmentioning

confidence: 99%

Empirical Mixing Model for the Electromagnetic Compatibility Analysis of On-Chip Interconnects

Holik¹

2012

Dielectric Material

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“…This implies that just congestion-driven global routing cannot address the wire density issue efficiently. Furthermore, we observe that wire delay is near linearly proportional to wire density in global routing even with CMP effect (dishing/erosion and dummy fill) [9,20,29] and scattering effect [15] taken into consideration.…”

mentioning

confidence: 88%

“…Especially, topography (thickness) variation after CMP is shown to be systematically determined by wire density distribution [19,21,29]. Even after CMP, intra-chip topography variation can still be on the order of 20-40% [9,21].…”

mentioning

confidence: 99%

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Wire density driven global routing for CMP variation and timing

Cho

Pan

Xiang

et al. 2006

Proceedings of the 2006 IEEE/ACM International Conference on Computer-Aided Design - ICCAD '06

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In this paper, we propose the first wire density driven global routing that considers CMP variation and timing. To enable CMP awareness during global routing, we propose a compact predictive CMP model with dummy fill, and validate it with extensive industry data. While wire density has some correlation and similarity to the conventional congestion metric, they are indeed different in the global routing context. Therefore, wire density rather than congestion should be a unified metric to improve both CMP variation and timing. The proposed wire density driven global routing is implemented in a congestion-driven global router [5] for CMP and timing optimization. The new global router utilizes several novel techniques to reduce the wire density of CMP and timing hotspots. Our experimental results are very encouraging. The proposed algorithm improves CMP variation and timing by over 7% with negligible overhead in wirelength and even slightly better routability, compared to the pure congestion-driven global router [5].

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“…The main reason for the copper CMP problems is wire density distribution. Higher wire density usually leads to copper thickness reduction due to erosion after CMP [14], [15]. Also, the reduced copper thickness after CMP can worsen the scattering effect, further increasing resistance [19].…”

Section: Manufacturability Aware Routingmentioning

confidence: 99%

Synergistic physical synthesis for manufacturability and variability in 45nm designs and beyond

Pan

Cho

2008

2008 Asia and South Pacific Design Automation Conference

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Abstract-Nanometer IC designs are increasingly challenged by manufacturing closure, i.e., being fabricated with high product yield, mainly due to aggressive technology scaling and increasing process/environmental variations. Realizing the criticality of addressing manufacturability for higher yield and tolerance to variations during design, there has been a surge of research activities recently from both academia and industry. In this paper, we will survey the key activities in synergistic physical synthesis and shed lights on some of the future research directions.

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Impact of interconnect pattern density information on a 90 nm technology ASIC design flow

Cited by 15 publications

References 9 publications

Empirical Mixing Model for the Electromagnetic Compatibility Analysis of On-Chip Interconnects

Empirical Mixing Model for the Electromagnetic Compatibility Analysis of On-Chip Interconnects

Wire density driven global routing for CMP variation and timing

Synergistic physical synthesis for manufacturability and variability in 45nm designs and beyond

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