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An interconnect distribution model for homogeneous, three-dimensional (3-D) architectures with variable separation of strata is presented. Three-dimensional architectures offer an opportunity to reduce the length of the longest interconnects. The separation of strata has little impact on the length of interconnects but a large impact on the number of interstratal interconnects. Using a multilevel interconnect methodology for an ITRS 2005 100 nm ASIC, a two-strata architecture offers a 3.9 increase in wire-limited clock frequency, an 84% decrease in wire-limited area or a 25% decrease in the number of metal levels required. In practice, however, such fabrication advances as improved alignment tolerances in wafer-bonding techniques are needed to gain key advantages stemming from 3-D architectures for homogeneous gigascale integrated circuits.Index Terms-Interconnections, modeling, multilevel systems, system analysis and design, system-level interconnect prediction, three-dimensional (3-D) architecture, wire-length distribution.

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A system-on-a-chip (SoC) contains several pre-designed heterogeneous megacells that have been designed and routed optimally. In this paper a new stochastic net-length distribution for global interconnects in a nonhomogeneous SoC is derived using novel models for netlist, placement, and routing information. The netlist information is rigorously derived based on heterogeneous Rent's rule, the placement information is modeled by assuming a random placement of terminals for a given net in a bounding area, and the routing information is constructed based on a new model for minimum rectilinear Steiner tree construction (MRST). The combination of the three models gives a priori estimation of global net-length distribution in a heterogeneous SoC. Unlike previous models that empirically relate the average length of the global wires to the chip area, the new distribution provides a complete and accurate distribution of net-length for global interconnects. Through comparison with actual product data, it is shown that the new stochastic model successfully predicts the global net-length distribution of a heterogeneous system.

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In systems on chip, the energy consumed by the Network on Chip (NoC) depends heavily on the network traffic pattern. The higher the communication locality, the lower the energy consumption will be. In this paper, we use the Communication Probability Distribution (CPD) to model communication locality and energy consumption in NoC. Firstly, based on recent results showing that communication patterns of many parallel applications follow Rent's rule [6], we propose a Rent's rule traffic generator. In this method, the probability of communication between cores is derived directly from Rent's rule, which results in CPDs displaying high locality. Next, we provide a model for predicting NoC energy consumption based on the CPD. The model was tested on two NoC systems and several workloads, including Rent's rule traffic, and obtained accurate results when compared to simulations. The results also show that Rent's rule traffic has lower energy consumption than commonly used synthetic workloads, due to its higher communication locality. Finally, we exploit the tunability of our traffic generator to study applications with different locality, analyzing the impact of the Rent's exponent on energy consumption.

While quantum dots-in-a-well (DWELL) infrared photodetectors have the feature that their spectral responses can be shifted continuously by varying the applied bias, the width of the spectral response at any applied bias is not sufficiently narrow for use in multispectral sensing without the aid of spectral filters. To achieve higher spectral resolutions without using physical spectral filters, algorithms have been developed for post-processing the DWELL's bias-dependent photocurrents resulting from probing an object of interest repeatedly over a wide range of applied biases. At the heart of these algorithms is the ability to approximate an arbitrary spectral filter, which we desire the DWELL-algorithm combination to mimic, by forming a weighted superposition of the DWELL's non-orthogonal spectral responses over a range of applied biases. However, these algorithms assume availability of abundant DWELL data over a large number of applied biases (>30), leading to large overall acquisition times in proportion with the number of biases. This paper reports a new multispectral sensing algorithm to substantially compress the number of necessary bias values subject to a prescribed performance level across multiple sensing applications. The algorithm identifies a minimal set of biases to be used in sensing only the relevant spectral information for remote-sensing applications of interest. Experimental results on target spectrometry and classification demonstrate a reduction in the number of required biases by a factor of 7 (e.g., from 30 to 4). The tradeoff between performance and bias compression is thoroughly investigated.

A global net-length distribution for three-dimensional system-on-a-chip architectures is derived to quantify the impact of the number of strata, or active layers, on the length of the long global interconnects.Model projections indicate a reduction in the global net length as the square root of the number of strata, thus enabling a significant reduction in chip footprint area, power dissipation, and global cycle time in comparison to a two-dimensional system-on-a-chip.Unlike its homogeneous counterpart, the vertical integration of a heterogeneous system is not limited by the density of interstratal interconnects.The size of the large megacells, especially memory, may restrict the effectiveness of a large number of strata.