Impact of three-dimensional architectures on interconnects in gigascale integration

Abstract

An interconnect distribution model for homogeneous, three-dimensional (3-D) architectures with variable separation of strata is presented. Three-dimensional architectures offer an opportunity to reduce the length of the longest interconnects. The separation of strata has little impact on the length of interconnects but a large impact on the number of interstratal interconnects. Using a multilevel interconnect methodology for an ITRS 2005 100 nm ASIC, a two-strata architecture offers a 3.9 increase in wire-limited clock frequency, an 84% decrease in wire-limited area or a 25% decrease in the number of metal levels required. In practice, however, such fabrication advances as improved alignment tolerances in wafer-bonding techniques are needed to gain key advantages stemming from 3-D architectures for homogeneous gigascale integrated circuits.Index Terms-Interconnections, modeling, multilevel systems, system analysis and design, system-level interconnect prediction, three-dimensional (3-D) architecture, wire-length distribution.

3-D Topologies for Networks-on-Chip

“…Furthermore, , , and are not necessarily equal. The average number of hops in a 3-D NoC is (2) assuming dimension-order routing such that the minimum distance paths are used for the routing of packets between any source-destination node pair.…”

“…The major advantage of 3-D ICs is the considerable reduction in the length and number of global interconnects, resulting in an increase in the performance and decrease in the power consumption and area of wire limited circuits [2], [3]. Another important advantage of 3-D ICs is that this paradigm enables the integration of CMOS circuits with disparate technologies which can be non-silicon or even electro-mechanical [4].…”

Effect of process variations in 3D global clock distribution networks

“…Multiplane circuits considerably reduce the interconnect length because of the vertical interconnections [Joyner et al 2001]. Considering the important synchronization issue, the reduced interconnect latency can be exploited to either relax the clock skew constraints or further increase the speed of a circuit.…”

Physical Design Issues in 3-D Integrated Technologies

“…The inherent advantage of 3-D integration is the drastic decrease in interconnect length, particularly the long global interconnects, which directly results in increased speed [3], [4], [5]. The interconnect power is also reduced as the capacitance of the wires decreases [6].…”