3-D Topologies for Networks-on-Chip

Pavlidis, Vasilis F.; Friedman, Eby G.

doi:10.1109/tvlsi.2007.893649

Cited by 341 publications

(139 citation statements)

References 33 publications

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“…As shown in Fig. 2, each tile is composed of a router and IP core(s) [2]. The IP core(s) could be a processor core, or a memory unit (e.g., L1 cache or L2 unit/bank), or a combination of them (for example, a tile can be composed of a processor, L1 data and instruction cache, and an L2 bank).…”

Section: -D Noc Architecturementioning

confidence: 99%

“…However, with the continued increase of the number of processing cores on a chip [1] enabled by the rapid advances in CMOS technology, standard NoCs will find that they are difficult to keep up the bandwidths and/or power consumption requirements as imposed by future super large SoCs. To address this pressing interconnect challenge, three dimensional NoCs have been proposed [2]. 3-D integration can considerably help reduce the lengths of global interconnects, resulting in significantly lower interconnection delay and power consumption as well as smaller chip area [3].…”

Section: Introductionmentioning

confidence: 99%

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Efficient multicast schemes for 3-D Networks-on-Chip

Wang

Yang

Jiang

et al. 2013

Journal of Systems Architecture

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a b s t r a c t 3-D Networks-on-Chip (NoCs) have been proposed as a potent solution to address both the interconnection and design complexity problems facing future System-on-Chip (SoC) designs. In this paper, two topology-aware multicast routing algorithms, Multicasting XYZ (MXYZ) and Alternative XYZ (AL + XYZ) algorithms in supporting of 3-D NoC are proposed. In essence, MXYZ is a simple dimension order multicast routing algorithm that targets 3-D NoC systems built upon regular topologies. To support multicast routing in irregular regions, AL + XYZ can be applied, where an alternative output channel is sought to forward/replicate the packets whenever the output channel determined by MXYZ is not available. To evaluate the performance of MXYZ and AL + XYZ, extensive experiments have been conducted by comparing MXYZ and AL + XYZ against a path-based multicast routing algorithm and an irregular region oriented multiple unicast routing algorithm, respectively. The experimental results confirm that the proposed MXYZ and AL + XYZ schemes, respectively, have lower latency and power consumption than the other two routing algorithms, meriting the two proposed algorithms to be more suitable for supporting multicasting in 3-D NoC systems. In addition, the hardware implementation cost of AL + XYZ is shown to be quite modest.

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Section: -D Noc Architecturementioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Efficient multicast schemes for 3-D Networks-on-Chip

Wang

Yang

Jiang

et al. 2013

Journal of Systems Architecture

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show abstract

“…In the area of designing NoC architectures for 3D ICs, most of the literature has focussed on regular 3D NoC topologies such as meshes [7][8][9][10][11], which are appropriate for regular 3D designs [12,13]. However, most modern SoC architectures consist of heterogenous cores such as CPU or DSP modules, video processors, and embedded memory blocks, and the traffic requirements among the cores can vary widely.…”

Section: Contributions Of Our Workmentioning

confidence: 99%

“…We use Orion [29] to estimate the power dissipation of the switches. The link power and delay are modeled based on the equations from Pavlidis et al [8], and the delay of switches are estimated using the model described in Section V-B. All switches and links are evaluated under a 45nm technology.…”

Section: A Experimental Setupmentioning

confidence: 99%

Application-specific 3D Network-on-Chip design using simulated allocation

Zhou¹,

Yuh²,

Sapatnekar³

2010

2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC)

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Abstract-Three-dimensional (3D) silicon integration technologies have provided new opportunities for Network-on-Chip (NoC) architecture design in Systems-on-Chip (SoCs). In this paper, we consider the application-specific NoC architecture design problem in a 3D environment. We present an efficient floorplanaware 3D NoC synthesis algorithm, based on simulated allocation, a stochastic method for traffic flow routing, and accurate power and delay models for NoC components. We demonstrate that this method finds greatly improved topologies for various design objectives such as NoC power (average savings of 34%), network latency (average reduction of 35%) and chip temperature (average reduction of 20%).

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“…For example, in [27], [28] alternate ways of interconnecting 3D chips are contrasted; namely, the authors focus on several variants of 3D meshes, stacked meshes, stacked tori, etc.. The main focus of the authors is on topologies and on performance metrics, while the physical implementation is not studied in depth.…”

Section: B Network-on-chipmentioning

confidence: 99%

Supporting vertical links for 3D networks-on-chip: toward an automated design and analysis flow

Loi

Angiolini

Benini

2007

Proceedings of the Second International Conference on Nano-Networks

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Abstract-Three-dimensional (3D) manufacturing technologies are viewed as promising solutions to the bandwidth bottlenecks in VLSI communication. At the architectural level, Networkson-chip (NoCs) have been proposed to address the complexity of interconnecting an ever-growing number of cores, memories and peripherals. NoCs are a promising choice for implementing scalable 3D interconnect architectures. However, the development of 3D NoCs is still at an early development stage. In this paper, we present a semi-automated design flow for 3D NoCs. Starting from an accurate physical and geometric model of ThroughSilicon Vias (TSVs), we extract a circuit-level model for vertical interconnections, and we use it to evaluate the design implications of extending switch architectures with ports in the vertical direction. In addition, we present a design flow allowing for post-layout simulation of NoCs with links in all three physical dimensions.

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3-D Topologies for Networks-on-Chip

Cited by 341 publications

References 33 publications

Efficient multicast schemes for 3-D Networks-on-Chip

Efficient multicast schemes for 3-D Networks-on-Chip

Application-specific 3D Network-on-Chip design using simulated allocation

Supporting vertical links for 3D networks-on-chip: toward an automated design and analysis flow

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