Supporting vertical links for 3D networks-on-chip: toward an automated design and analysis flow

Abstract

Abstract-Three-dimensional (3D) manufacturing technologies are viewed as promising solutions to the bandwidth bottlenecks in VLSI communication. At the architectural level, Networkson-chip (NoCs) have been proposed to address the complexity of interconnecting an ever-growing number of cores, memories and peripherals. NoCs are a promising choice for implementing scalable 3D interconnect architectures. However, the development of 3D NoCs is still at an early development stage. In this paper, we present a semi-automated design flow for 3D NoCs. Starting from an accurate physical and geometric model of ThroughSilicon Vias (TSVs), we extract a circuit-level model for vertical interconnections, and we use it to evaluate the design implications of extending switch architectures with ports in the vertical direction. In addition, we present a design flow allowing for post-layout simulation of NoCs with links in all three physical dimensions.

Comparative Analysis of NoCs for Two-Dimensional Versus Three-Dimensional SoCs Supporting Multiple Voltage and Frequency Islands

“…For reference, the power consumption (with 100% switching activity), area, and maximum operating frequency for some of the components are presented in Table I. In [26], the authors show that the power consumption of tightly packed TSVs is smaller than that of horizontal interconnect by two orders of magnitude. Therefore, the impact of power consumption and delay of the vertical links is negligible, as they are very short as well (15-25 μm).…”

Characterization and Implementation of Fault-Tolerant Vertical Links for 3-D Networks-on-Chip

“…5) after the network, and the outcome is summarized in Table I. As can be seen, misalignments of even noticeable entity do not normally compromise functionality and have a minimum impact on delay, which is usually dominated by the overall planar routing parasitics [19]. Extreme misalignments, like in the last row of Table I, are highly unlikely in state-of-the-art wafer bonding processes [2], [3], [27].…”

“…In this paper, we propose both a detailed characterization of the vertical links and switches, and a novel scheme to overcome the yield limitation. The starting point of this paper is [19], [20], where a thorough physical and timing analysis of the vertical links has been conducted on a real 3-D NoC. Further, it is worth stressing that the proposed scheme can also be applied successfully to alternative interconnection schemes, such as buses.…”

“…Starting from these considerations and based on [19], we have conducted a detailed study to quantify the impact of TSV failures on overall chip yield. To this end, we use our electrical model of tiers interconnected by TSVs (Fig.…”

Vertical interconnects squeezing in symmetric 3D mesh Network-on-Chip

“…communication-centric interconnect architecture based on network-on-chip (NoC) that addresses scalability challenges as well as bandwidth bottleneck [1][2] and three dimensional integrated circuits (3D ICs) that alleviate interconnect latency pressure as well as heterogeneous integration problems [3] [4] [5] [6], are emerging for such complex integrated systems. 3D NoCs combining both the benefits soon become one of the most promising on-chip communication techniques in complex System-on-Chip (SoC) [7] [8].…”