Vertical interconnects squeezing in symmetric 3D mesh Network-on-Chip

Liu, Ming; Zhang, Bo; Han, Sang-Min; Li, Qing

doi:10.1109/aspdac.2011.5722213

Cited by 46 publications

(28 citation statements)

References 21 publications

(21 reference statements)

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“…However, they still require a large number of vertical interconnects and a rather optimistic TSV induced area consumption is assummed. In [20] the authors propose a scheme where multiple routers share a common TSV array for intra layer NoC links. Access to the TSV array is granted by an arbiter.…”

Section: Related Workmentioning

confidence: 99%

TSV-virtualization for Multi-protocol-Interconnect in 3D-ICs

Miller¹,

Wild²,

Herkersdorf³

2012

2012 15th Euromicro Conference on Digital System Design

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Abstract-Through Silicon Vias (TSVs) are the method of choice to realize vertical connections between different chip layers in three dimensional Integrated Circuits (3D-ICs). These TSVs offer a fast connection and due to their short wire length, only a small capacitive load to the driving circuitry. On the other hand TSVs consume a relative large amount of chip area and as TSVcount increases the overall yield generally drops due to TSV manufacturing difficulties. As a result of the low capacitance, TSVs can be clocked much higher than conventional intralayer links. To fully utilize the TSV-based vertical bandwidth we propose using them in a multiplexed manner and share them between several virtual links. On top of that we propose using TSVs to stretch state-of-the art interconnects like busses, crossbars or NoCs to other silicon layers in the 3D stack. This reduces TSV count and gives designers the opportunity to easily migrate from 2D to 3D designs and to largely benefit from reuse of existing IP blocks and interconnection schemes.

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Section: Related Workmentioning

confidence: 99%

TSV-virtualization for Multi-protocol-Interconnect in 3D-ICs

Miller¹,

Wild²,

Herkersdorf³

2012

2012 15th Euromicro Conference on Digital System Design

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“…But it increases the complexity and area of router because of the converters between parallel and serial mode. The squeezing scheme is proposed to minimize the amount of TSV by applying sharing logics between current and destination layers [4]. The packets have to reserve all of the TSV sharing logics for inter-layer communication.…”

Section: Motivationsmentioning

confidence: 99%

H-cluster: a hybrid architecture for three-dimensional many-core chips

Sun

Yang

et al. 2014

IEICE Electron. Express

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With more and more cores integrated in a single chip, threedimensional network-on-chip (3D NoC) based on through-silicon-via (TSV) is a good way to deal with the problem of large network diameter. But if the number of cores increase to several hundreds or even thousands, the large number of TSV cannot be neglected any more due to the low yield and high overhead of TSV. Therefore, it is necessary to obtain a balance point between cost and performance. In this letter, we propose H-cluster that applies a hybrid vertical interconnect scheme. It minimizes the number of TSV by sharing vertical links through vertical routers. The simulation results shows that the H-cluster can improve the yield of many-cores chip and provide a better performance.

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“…As SoC complexity increases with 3D Integrated Circuit (IC) technology scaling, existing general simulation platforms, software-based or hardware-based, are far from being suited for large systems. Several SystemC based environments have been proposed to perform 3D NoC modeling and simulation at the system level [3,4]. However, these software-based solutions compromise between cycle accuracy and simulation speed.…”

Section: Introductionmentioning

confidence: 99%

Dynamically reconfigurable simulation platform for 3D NoC based on multi-FPGA

Zheng

Gao

et al. 2015

IEICE Electron. Express

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Taking advantage of Three Dimension (3D) Integrated Circuit (IC) technology, 3D Network-on-Chip (NoC) is becoming a promising architecture of high-performance System-on-Chip (SoC). To model 3D NoC and to evaluate the performance fast and accurately, the simulation method is therefore critical issue. Compared to software simulation, Field Programmable Gate Array (FPGA) based simulation can offer a high speed validation process with a higher accuracy. But there still exist some difficulties such as partition, scalability and so on. This paper proposed a novel multi-FPGA simulation platform, RcEF3Ns (Reconfigurable Simulation on multi-FPGA for 3D NoCs), based on Xilinx Virtex-6 FPGAs. The design method of RcEF3Ns employs a single FPGA to manage vertical transaction independently, supporting bus and network communication mechanism. All the parameters can be dynamically reconfigured on-chip to model 3D NoC architecture without re-synthesizing. The experiments show RcEF3Ns' speedups over 10 times without sacrificing accuracy when compared to other hardware based platform.

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Vertical interconnects squeezing in symmetric 3D mesh Network-on-Chip

Cited by 46 publications

References 21 publications

TSV-virtualization for Multi-protocol-Interconnect in 3D-ICs

TSV-virtualization for Multi-protocol-Interconnect in 3D-ICs

H-cluster: a hybrid architecture for three-dimensional many-core chips

Dynamically reconfigurable simulation platform for 3D NoC based on multi-FPGA

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