Comparative Analysis of NoCs for Two-Dimensional Versus Three-Dimensional SoCs Supporting Multiple Voltage and Frequency Islands

Seiculescu, Ciprian; Murali, Srinivasan; Benini, Luca; Micheli, Giovanni De

doi:10.1109/tcsii.2010.2047320

Cited by 14 publications

(5 citation statements)

References 28 publications

(35 reference statements)

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“…However, most of the existing VFI methodologies for TSV-based 3D NoC ignores the performance-thermal tradeoffs (Seiculescu et al 2010;Rahmani et al 2013). For VFI-based system, a group of cores with similar communication and computation characteristics are clustered together.…”

Section: Performance and Thermal-efficient 3d Noc Incorporating Vfimentioning

confidence: 99%

Performance and Thermal Tradeoffs for Energy-Efficient Monolithic 3D Network-on-Chip

Das

Doppa

Pande

et al. 2018

ACM Trans. Des. Autom. Electron. Syst.

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Three-dimensional (3D) integration enables the design of high-performance and energy-efficient network on chip (NoC) architectures as communication backbones for manycore chips. To exploit the benefits of the vertical dimension of 3D integration, through-silicon-via (TSV) has been predominantly used in state-of-the-art manycore chip design. However, for TSV-based systems, high power density and the resultant thermal hotspot remain major concerns from the perspectives of chip functionality and overall reliability. The power consumption and thermal profiles of 3D NoCs can be improved by incorporating a Voltage-Frequency-Island (VFI)-based power management strategy. However, due to inherent thermal constraints of a TSV-based 3D system, we are unable to fully exploit the benefits offered by the power management methodology. In this context, emergence of monolithic 3D (M3D) integration has opened up new possibility of designing ultra-low-power and high-performance circuits and systems. The smaller dimensions of the inter-layer dielectric (ILD) and monolithic inter-tier vias (MIVs) offer high-density integration, flexibility of partitioning logic blocks across multiple tiers, and significant reduction of total wire-length. In this work, we present the first-ever study of the performance-thermal tradeoffs for energy efficient monolithic 3D manycore chips. In particular, we present a comparative performance evaluation of M3D NoCs with respect to their conventional TSV-based counterparts. We demonstrate that the proposed M3D-based NoC architecture incorporating VFI-based power management achieves a maximum of 29.4% lower energy-delay-product (EDP) compared to the TSV-based designs for a large set of benchmarks. We also demonstrate that the M3D-based NoC shows up to 29.1% lower maximum temperature than the TSV-based counterpart for these benchmarks.

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Section: Performance and Thermal-efficient 3d Noc Incorporating Vfimentioning

confidence: 99%

Performance and Thermal Tradeoffs for Energy-Efficient Monolithic 3D Network-on-Chip

Das

Doppa

Pande

et al. 2018

ACM Trans. Des. Autom. Electron. Syst.

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“…First, for voltage and frequency islands NoC-based systems, network partitioning techniques were used to divide the whole systems into partitions that were implemented as separate islands [28,29]. The use of partitioning with voltage and frequency island NoC-based systems was evaluated in [30]. Second, for multicast 2D NoCs routing, network partitioning techniques were used to enhance the bandwidth efficiency and the overall performance of NoC-based systems in [31,32].…”

Section: Related Workmentioning

confidence: 99%

Networks-on-Chip Architecture Customization using Network Partitioning: A System-Level Performance Evaluation

Morgan¹

2015

IJCDS

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Networks-on-Chip (NoC) design is a trade-off between cost and performance. To realize the best trade-off between these factors, researchers have recently proposed using network partitioning techniques to customize the NoC architecture according to the application requirements. In this paper, the impact of using partitioning on different NoC metrics; namely, power, area, and delay, is analyzed. We present a system-level methodology to evaluate the performance of using partitioning-based architecture customization techniques with NoC. Our methodology is applied onto synthetic traffic as well as a number of real NoC benchmarks with different number of cores. Finally, we mathematically formulate evaluation factors that could be used as measures of the enhancements achieved by using partitioning.

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“…Impacts of single and multiple VFIs on system performance was analyzed in [19]. VFI partitioning scheme was proposed in [20]. Huang et al [21] proposed task allocation and scheduling algorithm for energy optimization targeting MPSoCs.…”

Section: Related Workmentioning

confidence: 99%

Post-Silicon Energy Optimization on Voltage-Frequency Island Based 3-D Multi-Core SoCs

Song

Liu

2014

AMM

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Technology scaling dramatically increases transistor integration capacity, enabling more and more cores to be integrated into a single chip. Parameter variability, however, leads to performance asymmetry among the cores, degrading the energy efficiency of the system. Recently, voltage/frequency island (VFI) based designs are widely exploited on a multi-core platform for system energy optimization under variations. In this paper, a post-silicon energy optimization scheme is proposed targeting VFI-based 3-D multi-core SoCs. Design constraints on VFI, difference of communication energies between horizontal and vertical directions and unique thermal feature of the 3-D chip are totally considered. An energy efficient task mapping and scheduling algorithm is proposed, which seamlessly combines with dynamic voltage/frequency scaling to minimize the system energy under deadline and thermal constraints. Experimental results demonstrate that the effectiveness of the proposed scheme.

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Comparative Analysis of NoCs for Two-Dimensional Versus Three-Dimensional SoCs Supporting Multiple Voltage and Frequency Islands

Cited by 14 publications

References 28 publications

Performance and Thermal Tradeoffs for Energy-Efficient Monolithic 3D Network-on-Chip

Performance and Thermal Tradeoffs for Energy-Efficient Monolithic 3D Network-on-Chip

Networks-on-Chip Architecture Customization using Network Partitioning: A System-Level Performance Evaluation

Post-Silicon Energy Optimization on Voltage-Frequency Island Based 3-D Multi-Core SoCs

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