Performance and Thermal Tradeoffs for Energy-Efficient Monolithic 3D Network-on-Chip

Abstract

Three-dimensional (3D) integration enables the design of high-performance and energy-efficient network on chip (NoC) architectures as communication backbones for manycore chips. To exploit the benefits of the vertical dimension of 3D integration, through-silicon-via (TSV) has been predominantly used in state-of-the-art manycore chip design. However, for TSV-based systems, high power density and the resultant thermal hotspot remain major concerns from the perspectives of chip functionality and overall reliability. The power consumption and thermal profiles of 3D NoCs can be improved by incorporating a Voltage-Frequency-Island (VFI)-based power management strategy. However, due to inherent thermal constraints of a TSV-based 3D system, we are unable to fully exploit the benefits offered by the power management methodology. In this context, emergence of monolithic 3D (M3D) integration has opened up new possibility of designing ultra-low-power and high-performance circuits and systems. The smaller dimensions of the inter-layer dielectric (ILD) and monolithic inter-tier vias (MIVs) offer high-density integration, flexibility of partitioning logic blocks across multiple tiers, and significant reduction of total wire-length. In this work, we present the first-ever study of the performance-thermal tradeoffs for energy efficient monolithic 3D manycore chips. In particular, we present a comparative performance evaluation of M3D NoCs with respect to their conventional TSV-based counterparts. We demonstrate that the proposed M3D-based NoC architecture incorporating VFI-based power management achieves a maximum of 29.4% lower energy-delay-product (EDP) compared to the TSV-based designs for a large set of benchmarks. We also demonstrate that the M3D-based NoC shows up to 29.1% lower maximum temperature than the TSV-based counterpart for these benchmarks.

Power Management of Monolithic 3D Manycore Chips with Inter-tier Process Variations

“…Power management in M3D-based manycore systems has been explored recently in Reference [13]. This work shows that an M3D-based system with power management achieves significant performance improvements with much lower EDP than its TSV-based counterpart.…”

“…This work shows that an M3D-based system with power management achieves significant performance improvements with much lower EDP than its TSV-based counterpart. It is also seen that the difference between the maximum and minimum temperatures in an M3D manycore system is insignificant [13]. However, the work presented in Reference [13] does not consider the effects of process variation or multi-tier processors enabled by M3D.…”

“…Voltage-frequency islands (VFI) is a popular power-management methodology that is applied to manycore chips [26,46]. VFIs have been demonstrated to be an important tool to improve the energy-efficiency and the thermal profile of M3D-based manycore designs [13]. However, state-of-the-art VFI-based power-management strategies for M3D systems are oblivious to the process-variation-induced performance degradations.…”

Taming extreme heterogeneity via machine learning based design of autonomous manycore systems

“…Third, to design optimized heterogeneous manycore systems, we need to trade-off multiple objectives including power, performance, thermal, and reliability resulting in a complex multi-objective design space exploration (MO-DSE) problem. The design optimization process should also account for the specific characteristics of emerging technologies [36,37].…”

Thermal-aware Dynamic Weighted Adaptive Routing Algorithm for 3D Network-on-Chip

“…Thermal-aware routing algorithms are classified in temporal and spatial routing algorithms. Temporal DTM (Dynamic Thermal Management) can dynamically adjust frequencies, voltages or clock cycles to reduce on-chip temperatures [12]. Usually a fully throttling scheme such as clock gating is applied to control the temperature of the thermal aggressive nodes.…”