Post-Silicon Energy Optimization on Voltage-Frequency Island Based 3-D Multi-Core SoCs

Abstract

Technology scaling dramatically increases transistor integration capacity, enabling more and more cores to be integrated into a single chip. Parameter variability, however, leads to performance asymmetry among the cores, degrading the energy efficiency of the system. Recently, voltage/frequency island (VFI) based designs are widely exploited on a multi-core platform for system energy optimization under variations. In this paper, a post-silicon energy optimization scheme is proposed targeting VFI-based 3-D multi-core SoCs. Design constraints on VFI, difference of communication energies between horizontal and vertical directions and unique thermal feature of the 3-D chip are totally considered. An energy efficient task mapping and scheduling algorithm is proposed, which seamlessly combines with dynamic voltage/frequency scaling to minimize the system energy under deadline and thermal constraints. Experimental results demonstrate that the effectiveness of the proposed scheme.