Characterization and Implementation of Fault-Tolerant Vertical Links for 3-D Networks-on-Chip

Loi, Igor; Angiolini, Federico; Fujita, Shinobu; Mitra, Subhasish; Benini, Luca

doi:10.1109/tcad.2010.2065990

Cited by 54 publications

(25 citation statements)

References 28 publications

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“…Such works dealt with this challenge by suggesting redundant TSV links [19], reliable routings [48]- [51], error detection/correction HW modules [52], or TSV-variationaware synthesis [53]. One approach for reliable routings, which is suitable for both 2-D and 3-D NoC interconnection network, is leveraging reconfigurable routing table to keep fault-tolerant routing paths [48], [49].…”

Section: Related Workmentioning

confidence: 99%

“…1 Note that the proposed architecture is only for a limited number of processing cores (equal or <32) because as the number of both cores and memory banks increases, the latency of the combinational interconnect increases (>10 ns, which is out of our scope). Scaling to larger number of processing cores (e.g., >32) requires building a multicluster fabric connected through a scalable NoC [19]. Scaling beyond that will require hierarchical multicluster schemes, and for extremely scaled architectures (1000 cores), hierarchical clustered multihop networks will have to be used.…”

mentioning

confidence: 99%

See 1 more Smart Citation

Cost-Effective Design of Mesh-of-Tree Interconnect for Multicore Clusters With 3-D Stacked L2 Scratchpad Memory

Kang

Benini

Micheli

2015

IEEE Trans. VLSI Syst.

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Abstract-3-D integrated circuits (3-D ICs) offer a promising solution to overcome the scaling limitations of 2-D ICs. However, using too many through-silicon-vias (TSVs) pose a negative impact on 3-D ICs due to the large overhead of TSV (e.g., large footprint and low yield). In this paper, we propose a new TSV sharing method for a circuit-switched 3-D mesh-of-tree (MoT) interconnect, which supports high-throughput and lowlatency communication between processing cores and 3-D stacked multibanked L2 scratchpad memory. The proposed method supports traffic balancing and TSV-failure tolerant routing. The proposed method advocates a modular design strategy to allow stacking multiple identical memory dies without the need for different masks for dies at different levels in the memory stack. We also investigate various parameters of 3-D memory stacking (e.g., fabrication technology, TSV bonding technique, number of memory tiers, and TSV sharing scheme) that affect interconnect latency, system performance, and fabrication cost. Compared to conventional MoT interconnect [6] that is straightforwardly adapted to 3-D integration, the proposed method yields up to ×2.11 and ×1.11 improvements in terms of cost efficiency (i.e., performance/cost) for microbump TSV bonding and direct Cu-Cu TSV bonding techniques, respectively. Index Terms-3-D integration, multicore, networks-on-chip (NoC), scratchpad memory (SPM).

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Section: Related Workmentioning

confidence: 99%

mentioning

confidence: 99%

Cost-Effective Design of Mesh-of-Tree Interconnect for Multicore Clusters With 3-D Stacked L2 Scratchpad Memory

Kang

Benini

Micheli

2015

IEEE Trans. VLSI Syst.

Self Cite

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“…6 illustrates the types of defects that the proposed scheme targets against. They include open defects and resistive open defects [20]- [22], [22]- [25], which bring about the chip delay or even complete damage. According to their locations, the defects can be categorized into two classes.…”

Section: Tolerable Faultsmentioning

confidence: 99%

Intra-channel Reconfigurable Interface for TSV and Micro Bump Fault Tolerance in 3-D RAMs

et al. 2014

2014 IEEE 23rd Asian Test Symposium

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Three-dimensional (3-D) integration using throughsilicon via (TSV) is an emerging technology for integrated circuit (IC) design. It has been used in DRAM die stacking extensively. However, yield remains a key issue for volume production of 3-D RAMs. In this paper, we present a point-to-point interconnection structure derived from bus and propose a faulttolerance interface scheme for TSVs and micro bumps to enhance their manufacturing yield in the 3-D RAMs. The interconnection structure is inherently redundant and thus can replace defective TSVs or micro bumps without using repair circuits. Global and local reconfiguration approaches are proposed which benefit distinct situations of the 3-D RAM. Analyses show that the proposed intra-channel reconfigurable interconnection scheme can improve the yield of the 3-D RAM effectively. Compared to the previous solution using an inter-channel reconfigurable interconnection scheme, the yield improvement can be as large as 23% which is very significant.

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“…The main issues regarding the use of TSVs are the large area overhead of TSV pitches, the yield reduction caused by the large number of TSVs, and TSV cost. Moreover, the manufacturing process of TSVs has become a main challenge due to the variability of the manufacturing process [2] [3]. The cost of high yield TSV manufacturing process is only justifiable in presence of a practical solution to counteract TSV related effects (such as voids in TSVs, TSV pinch-off, oxide defects such as pinholes, thermo-mechanical stress, cracks in microbumps, chip warpage, and impurities [4]) which may render the entire chip useless [5].…”

Section: Introductionmentioning

confidence: 99%

CoBRA: Low cost compensation of TSV failures in 3D-NoC

Salamat

Ebrahimi

Bagherzadeh

et al. 2016

2016 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)

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Abstract-3D-NoC has emerged to provide fast and power efficient connection between the layers of 2D-NoCs using Through-Silicon-Vias (TSV). Thermal stress, warpage, impurities and misalignment during the manufacturing process make these expensive TSVs vulnerable to faults. Chips with faulty TSVs should be either discarded or utilized by providing a proper fault-tolerant method. In this paper, we target designing a reconfigurable fault-tolerant routing algorithm capable of tolerating fabrication-time or run-time TSV failures. The proposed algorithm ensures a fault-free communication between any two nodes in the presence of TSV failures. Experimental results show that the proposed fault-tolerant routing algorithm provides 100% reliability as long as there is one healthy TSV in the eastmost or westmost column. The reliability of the counterpart algorithm, the Elevator-first routing algorithm, drops to 75% and 45% in presence of one and two faulty TSVs, respectively.

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Characterization and Implementation of Fault-Tolerant Vertical Links for 3-D Networks-on-Chip

Cited by 54 publications

References 28 publications

Cost-Effective Design of Mesh-of-Tree Interconnect for Multicore Clusters With 3-D Stacked L2 Scratchpad Memory

Cost-Effective Design of Mesh-of-Tree Interconnect for Multicore Clusters With 3-D Stacked L2 Scratchpad Memory

Intra-channel Reconfigurable Interface for TSV and Micro Bump Fault Tolerance in 3-D RAMs

CoBRA: Low cost compensation of TSV failures in 3D-NoC

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