Graphene nanoribbons (GNRs) with widths down to 16 nm have been characterized for their currentcarrying capacity. It is found that GNRs exhibit an impressive breakdown current density, on the order of 10 8 A/cm 2 . The breakdown current density is found to have a reciprocal relationship to GNR resistivity and the data fit points to Joule heating as the likely mechanism of breakdown. The superior current-carrying capacity of GNRs will be valuable for their application in on-chip electrical interconnects. The thermal conductivity of sub-20 nm graphene ribbons is found to be more than 1000 W/m-K.Keywords: Graphene, Breakdown current density, Nano ribbons, Maximum current * raghu@gatech.edu, Ph: 404 385 6463 2 Graphene is a promising electronic material because of many interesting properties like ballistic transport 1 , high intrinsic mobility 2 , and width-dependent bandgap 3 . Graphene, in its 2D form, has been shown to have a high thermal conductivity 4 of around 5000 W/m-K pointing to its potential use as an on-chip heat spreader.Graphene nano ribbons (GNRs) have been predicted to be superior to Cu in terms of resistance per unit length 5 for use as on-chip interconnects. A high current-carrying capacity is critical for interconnect applications and reliability. There have been a number of studies on carbon nanotube (CNT) breakdown current density, and the current-carrying capacity of single-walled CNTs 6 is found to be on the order of 10 8 A/cm 2 ; in carbon nanofibers, the breakdown current density (J BR ) has been measured 7 to be around 5x10 6 A/cm 2 . Electrical breakdown has been used to burn away successive shells in a multi-wall CNT 8,9 . More recently, electrical breakdown has been used to obtain semiconducting CNTs from a mixture of CNTs since metallic ones burn away at a lower breakdown voltage 10 . Theoretical projections suggest that J BR of graphene should be on the same order as for CNTs. However, little experimental evidence exists on the electrical breakdown of either 2D graphene or 1D GNRs. In this work, it is experimentally shown that GNRs demonstrate an impressive J BR . A simple relation between J BR and nanowire resistivity is seen to emerge from the experimental data.Few-layer graphene (1-5 layers) is used as the starting material (see supporting material 11 ).Each device consists of parallel ribbons fabricated between sets of electrodes, Fig. 1. The ribbon width between a pair of electrodes is designed to be the same for all the parallel ribbons. The range of widths studied in this work is 16nm
Abstract-Based on Rent's Rule, a well-established empirical relationship, a rigorous derivation of a complete wire-length distribution for on-chip random logic networks is performed. This distribution is compared to actual wire-length distributions for modern microprocessors, and a methodology to calculate the wire-length distribution for future gigascale integration (GSI) products is proposed.
Throughout the past four decades, silicon semiconductor technology has advanced at exponential rates in both performance and productivity. Concerns have been raised, however, that the limits of silicon technology may soon be reached. Analysis of fundamental, material, device, circuit, and system limits reveals that silicon technology has an enormous remaining potential to achieve terascale integration (TSI) of more than 1 trillion transistors per chip. Such massive-scale integration is feasible assuming the development and economical mass production of double-gate metal-oxide-semiconductor field effect transistors with gate oxide thickness of about 1 nanometer, silicon channel thickness of about 3 nanometers, and channel length of about 10 nanometers. The development of interconnecting wires for these transistors presents a major challenge to the achievement of nanoelectronics for TSI.
Twenty-first century opportunities for GSI will be governed in part by a hierarchy of physical limits on interconnects whose levels are codified as fundamental, material, device, circuit, and system. Fundamental limits are derived from the basic axioms of electromagnetic, communication, and thermodynamic theories, which immutably restrict interconnect performance, energy dissipation, and noise reduction. At the material level, the conductor resistivity increases substantially in sub-50-nm technology due to scattering mechanisms that are controlled by quantum mechanical phenomena and structural/morphological effects. At the device and circuit level, interconnect scaling significantly increases interconnect crosstalk and latency. Reverse scaling of global interconnects causes inductance to influence on-chip interconnect transients such that even with ideal return paths, mutual inductance increases crosstalk by up to 60% over that predicted by conventional RC models. At the system level, the number of metal levels explodes for highly connected 2-D logic megacells that double in size every two years such that by 2014 the number is significantly larger than ITRS projections. This result emphasizes that changes in design, technology, and architecture are needed to cope with the onslaught of wiring demands. One potential solution is 3-D integration of transistors, which is expected to significantly improve interconnect performance. Increasing the number of active layers, including the use of separate layers for repeaters, and optimizing the wiring network, yields an improvement in interconnect performance of up to 145% at the 50-nm node.
scite is a Brooklyn-based organization that helps researchers better discover and understand research articles through Smart Citations–citations that display the context of the citation and describe whether the article provides supporting or contrasting evidence. scite is used by students and researchers from around the world and is funded in part by the National Science Foundation and the National Institute on Drug Abuse of the National Institutes of Health.