Prediction of net-length distribution for global interconnects in a heterogeneous system-on-a-chip

Zarkesh-Ha, Payman; Davis, Jeffrey A.; Meindl, J.D.

doi:10.1109/92.902259

“…We use the Elmore delay, along with different wire delays at different levels of partitioning to achieve a more realistic delay model. Our interconnect delay model incorporates a statistical net-length estimation [11]. All these make our timing-driven partitioning algorithm fast and more reliable.…”

Section: Previous Workmentioning

confidence: 99%

“…where α, β, and γ are fitting parameters computed in [11] as α ≈ 1.1, β ≈ 2.0, and γ ≈ 0.5. During recursive partitioning, when a net is cut, it is assigned a certain wire delay that will be used to re-compute all delays on the paths that include that net.…”

Section: Delay Modelmentioning

confidence: 99%

See 1 more Smart Citation

Multi-objective circuit partitioning for cutsize and path-based delay minimization

Ababei¹,

Navaratnasothie

²

,

Bazargan

³

et al. 2002

Proceedings of the 2002 IEEE/ACM International Conference on Computer-Aided Design - ICCAD '02

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-In this paper we present multi-objective hMetis partitioning for simultaneous cutsize and circuit delay minimization. We change the partitioning process itself by introducing a new objective function that incorporates a truly path-based delay component for the most critical paths. To avoid semi-critical paths from becoming critical, the traditional slackbased delay component is also included in the cost function. The proposed timing driven partitioning algorithm is built on top of the hMetis algorithm, which is very efficient. Simulations results show that 14% average delay improvement can be obtained. Smooth trade-off between cutsize and delay is possible in our algorithm.

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“…In this study, due to lack of placement and routing tools supporting 3D heterogeneous architectures, we utilize the heterogeneous Rent's rule [18] for estimation. Consequently the vertical channel width, WV , should be equal to…”

Section: Estimating Total Tsv Areamentioning

confidence: 99%

High-performance, cost-effective heterogeneous 3D FPGA architectures

Le

¹

,

Reda

²

,

Bahar

³

2009

Proceedings of the 19th ACM Great Lakes Symposium on VLSI

5

0

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In this paper, we propose novel architectural and design techniques for three-dimensional field-programmable gate arrays (3D FPGAs) with Through-Silicon Vias (TSVs). We develop a novel design partitioning methodology that maps the heterogeneous computational resources of an FPGA into a number of die such that the total die area is minimized and the FPGA performance is maximized. Minimizing the total die area leads to direct manufacturing cost savings which is an important incentive to bring 3D technology to the fab and onto the market. An estimation framework is developed to assess the impact of silicon area utilized by 3D interconnect resources while taking into account the large area occupied by TSVs which is crucial to total die area of 3D FPGAs. In order to improve area and performance of 3D FPGAs, we design a novel 3D switch box with bypass TSVs. We also analyze the impact of different partitioning strategies on die area and find the optimal number of die that gives the largest reductions in total die area while maximizing the performance. Using a well-developed simulation infrastructure, we show that our methodologies can achieve an average reduction of 27.7% in total die area with a reduced interconnect path delay of about 58%.

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“…In this paper we utilize the estimation model for the global wiring requirement for heterogeneous networks developed by Zarkesh-Ha et al [18], where the total wire length is computed as…”

Section: Estimating Total Routing Areamentioning

confidence: 99%

High-performance, cost-effective heterogeneous 3D FPGA architectures

Le

¹

,

Reda

²

,

Bahar

³

2009

Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays

View full text Add to dashboard Cite

In this paper, we propose novel architectural and design techniques for three-dimensional field-programmable gate arrays (3D FPGAs) with Through-Silicon Vias (TSVs). We develop a novel design partitioning methodology that maps the heterogeneous computational resources of an FPGA into a number of die such that the total die area is minimized and the FPGA performance is maximized. Minimizing the total die area leads to direct manufacturing cost savings which is an important incentive to bring 3D technology to the fab and onto the market. An estimation framework is developed to assess the impact of silicon area utilized by 3D interconnect resources while taking into account the large area occupied by TSVs which is crucial to total die area of 3D FPGAs. In order to improve area and performance of 3D FPGAs, we design a novel 3D switch box with bypass TSVs. We also analyze the impact of different partitioning strategies on die area and find the optimal number of die that gives the largest reductions in total die area while maximizing the performance. Using a well-developed simulation infrastructure, we show that our methodologies can achieve an average reduction of 27.7% in total die area with a reduced interconnect path delay of about 58%.

show abstract

Prediction of net-length distribution for global interconnects in a heterogeneous system-on-a-chip

Cited by 57 publications

References 24 publications

Multi-objective circuit partitioning for cutsize and path-based delay minimization

Multi-objective circuit partitioning for cutsize and path-based delay minimization

High-performance, cost-effective heterogeneous 3D FPGA architectures

High-performance, cost-effective heterogeneous 3D FPGA architectures

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