In this paper, we propose novel architectural and design techniques for three-dimensional field-programmable gate arrays (3D FPGAs) with Through-Silicon Vias (TSVs). We develop a novel design partitioning methodology that maps the heterogeneous computational resources of an FPGA into a number of die such that the total die area is minimized and the FPGA performance is maximized. Minimizing the total die area leads to direct manufacturing cost savings which is an important incentive to bring 3D technology to the fab and onto the market. An estimation framework is developed to assess the impact of silicon area utilized by 3D interconnect resources while taking into account the large area occupied by TSVs which is crucial to total die area of 3D FPGAs. In order to improve area and performance of 3D FPGAs, we design a novel 3D switch box with bypass TSVs. We also analyze the impact of different partitioning strategies on die area and find the optimal number of die that gives the largest reductions in total die area while maximizing the performance. Using a well-developed simulation infrastructure, we show that our methodologies can achieve an average reduction of 27.7% in total die area with a reduced interconnect path delay of about 58%.
Energy efficiency is now a critically important design constraint for most computing systems today. Likewise, reliability has always been a top concern, from high-performance systems to mobile embedded applications. However, as technological advances produce devices only a few nanometers in length, and applications become more memory-and compute-intensive, energy-efficiency and reliability become harder to manage. In this talk, I will present techniques-past and present-across the HW/SW stack, for energy-efficient and reliable computing. I will also discuss how these techniques may be used to achieve more sustainable computing in the future. Bio: R. Iris Bahar received the B.S. and M.S. degrees in computer engineering from the University of Illinois, Urbana-Champaign, and the Ph.D. degree in electrical and computer engineering from the University of Colorado, Boulder. Before entering the Ph.D program at CU-Boulder, she was with Digital Equipment Corporation, responsible for the hardware implementation of the memory controller unit for their NVAX processor. She has been on the faculty at Brown University in the School of Engineering since 1996, and now holds a dual appointment as Professor of Engineering and Professor of Computer Science. Her research interests include computer architecture; computer-aided design for synthesis, verification and low-power applications; design, test, and reliability issues for nanoscale systems; and most recently, design of robotic systems. Her research has been continuously funded since 1997 through various industrial and government sources, including the NSF, DARPA, DoD, the Semiconductor Research Corporation (SRC), Intel, IBM and NASA.
scite is a Brooklyn-based organization that helps researchers better discover and understand research articles through Smart Citations–citations that display the context of the citation and describe whether the article provides supporting or contrasting evidence. scite is used by students and researchers from around the world and is funded in part by the National Science Foundation and the National Institute on Drug Abuse of the National Institutes of Health.
hi@scite.ai
10624 S. Eastern Ave., Ste. A-614
Henderson, NV 89052, USA
Copyright © 2024 scite LLC. All rights reserved.
Made with 💙 for researchers
Part of the Research Solutions Family.