High-performance, cost-effective heterogeneous 3D FPGA architectures

Abstract

In this paper, we propose novel architectural and design techniques for three-dimensional field-programmable gate arrays (3D FPGAs) with Through-Silicon Vias (TSVs). We develop a novel design partitioning methodology that maps the heterogeneous computational resources of an FPGA into a number of die such that the total die area is minimized and the FPGA performance is maximized. Minimizing the total die area leads to direct manufacturing cost savings which is an important incentive to bring 3D technology to the fab and onto the market. An estimation framework is developed to assess the impact of silicon area utilized by 3D interconnect resources while taking into account the large area occupied by TSVs which is crucial to total die area of 3D FPGAs. In order to improve area and performance of 3D FPGAs, we design a novel 3D switch box with bypass TSVs. We also analyze the impact of different partitioning strategies on die area and find the optimal number of die that gives the largest reductions in total die area while maximizing the performance. Using a well-developed simulation infrastructure, we show that our methodologies can achieve an average reduction of 27.7% in total die area with a reduced interconnect path delay of about 58%.

Three-Dimensional Tree-Based FPGA: Architecture Exploration Tools and Technologies

“…In order to have a detailed path delay analysis and architecture optimization, we used the optimal vertical and horizontal [27] shows 58 % performance improvement. However the paper lacks the hardware infrastructure to experiment and validate the achievement presented in it.…”

“…As explained in [4,9,27] the programmable interconnect overhead is main design element to increase the FPGA system performance. The main advantage of horizontally partitioned 3D heterogeneous Tree-based FPGA, is that, it offers design flexibility to optimize the wire length of higher levels of the Tree interconnects.…”

High performance 3-dimensional heterogeneous tree-based FPGA architectures (HT-FPGA)

“…The architecture definition, partitioning, placement, routing and optimization are performed individually for each netlist listed in Table 1. To make 3D HT-FPGA more efficient in terms of design and manufacturing, it is essential to minimize the TSV count because TSV consumes more silicon area than horizontal interconnects [9,5]. The TSV and architecture optimization are performed based on Rent's parameter [7] "p" defined for a Tree-based heterogeneous architecture as shown in equation 1.…”

“…Nonetheless the number of available TSVs within 3D-SBs is assumed to be fixed and that means the design do not investigate the impact of different numbers of TSVs in a 3D-SB. A mesh-based heterogeneous 3D FPGA architecture optimization is presented in [5]. …”

Domain-specific processor with 3D integration for medical image processing

“…In the context of GPPs, interface between the L2 cache and main memory is architected using 3D interconnect technology, and performance is compared to a 2D design for memoryintensive applications [6][7][8][9][10]. In the context of FPGAs, a number of recent studies have shown that 3D FPGAs have better performance than existing 2D designs [11][12][13].…”