Characterization and modeling of clock skew with process variations

Zarkesh-Ha, Payman; Mule, T.; Meindl, J.D.

doi:10.1109/cicc.1999.777319

Cited by 55 publications

(28 citation statements)

References 7 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…When we consider the situation with branch loads, i.e., k $ 0, the properties on dt dy for Equation (3) do not change and the wire shape is same as in Figure 5 and the value of p is determined by: (9) Even though the wire shape in Figure 5 looks strange, it may happen in reality. If the path is routed in an L-shape with a horizontal and a vertical segment, the two segments are usually on different metal layers.…”

Section: The Maximum Delay Wire Shap-ingmentioning

confidence: 99%

“…Realizing the great importance of process variations, many works have been carried out to model their effect [10,7,2,9,15,1,17,14]. One major objective of these modeling works is to find a reliable estimation on the worst case timing performance induced by process variations, either the worst delay along timing critical paths in timing analysis or the worst skew in a clock network.…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Analytical bound for unwanted clock skew due to wire width variation

Rajaram

Liu

et al. 2006

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

View full text Add to dashboard Cite

Under modern VLSI technology, process variations greatly affect circuit performance, especially clock skew which is very timing sensitive. Unwanted skew due to process variation forms a bottleneck preventing further improvement on clock frequency. Impact from intra-chip interconnect variation is becoming remarkable and is difficult to be modeled efficiently due to its distributive nature. Through wire shaping analysis, we establish an analytical bound for the unwanted skew due to wire width variation which is the dominating factor among interconnect variations. Experimental results on benchmark circuits show that this bound is safer, tighter and computationally faster than similar existing approach.

show abstract

Section: The Maximum Delay Wire Shap-ingmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Analytical bound for unwanted clock skew due to wire width variation

Rajaram

Liu

et al. 2006

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

View full text Add to dashboard Cite

show abstract

“…In general, the top-level segments of the tree are wider than the lower level segments. Furthermore, the top-level global segments of the tree are assigned to the upper metal layers and low-level local segments are routed using the lower metal layers [33].…”

Section: Temperature-dependent Zero Skew Clock Routing Methodologymentioning

confidence: 99%

Modeling and analysis of nonuniform substrate temperature effects on global ULSI interconnects

Ajami

Banerjee

Pedram

2005

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

182

143

View full text Add to dashboard Cite

Non-uniform thermal profiles on the substrate in high-performance ICs can significantly impact the performance of global on-chip interconnects. This paper presents a detailed modeling and analysis of the interconnect performance degradation due to the non-uniform temperature profiles that are encountered along long metal interconnects as a result of existing thermal gradients in the underlying Silicon substrate.A non-uniform temperature-dependent distributed RC interconnect delay model is proposed. The model is applied to a wide variety of interconnect layouts and substrate temperature distributions to quantify the impact of such thermal non-uniformities on signal integrity issues including speed degradation in global interconnect lines and skew fluctuations in clock signal distribution networks. Subsequently, a new thermally dependent zero-skew clock routing methodology is presented. This study suggests that thermally-aware analysis should become an integrated part of the various optimization steps in physicalsynthesis flow to improve the performance and integrity of signals in global ULSI interconnects.

show abstract

“…Skew is the most important of the signal integrity parameters for a clock distribution system [13]. Jitter, impedance mismatch, and noise of the RCD network are discussed in the following sections.…”

Section: A Clock Skewmentioning

confidence: 99%

Over GHz low-power RF clock distribution for a multiprocessor digital system

Ryu

Wai²,

Fan³

et al. 2001

2001 Proceedings. 51st Electronic Components and Technology Conference (Cat. No.01CH37220)

View full text Add to dashboard Cite

Abstract-Conventional interconnections for digital clock distribution pose a severe power consumption problem for GHz clock distribution, because of transmission line losses. They also pose difficult signal integrity problems because of clock skew, clock jitter, and signal reflection. To overcome these conventional digital clock distribution limitations, optical clock distribution techniques, based on guided-wave optics and free-space optics, have been proposed. However, optical clock distribution is bulky, difficult to fabricate, and expensive, even though it has lower power consumption and excellent signal integrity properties. Therefore, we have proposed a RF clock distribution (RCD) scheme for high-speed digital applications, in particular a multiprocessor system using global clocking. This paper first reports system power and signal integrity analysis results including skew, jitter, impedance mismatch, and noise for RF clock distribution, especially in the GHz range. Based on this analysis, a novel signal integrity design methodology for RF clock distribution systems is proposed. The clock skew created by process parameter variations are modeled and predicted. The system comprises a RF clock transmitter as a clock generator, an -tree with junction couplers as a clock distributing network and a RF receiver as a digital clock-recovery module. Flip-chip interconnections for the chip-to-substrate assembly and 0.35 m TSMC CMOS technology for the RF clock receiver are assumed. EMI analysis for 2 GHz 16-node board-level RF clock distribution networks is conducted using 3-D full-wave electromagnetic (EM) simulation. Finally, the RCD as a low power and high performance clocking method is demonstrated using HP's Advanced Design System (ADS) simulation, considering microwave frequency interconnection models and process parameter variations. In addition, test vehicles for both 2 GHz 16-node and 5 GHz 64-node board-level RF clock distribution networks were implemented and measured using thin, low-loss, and low permittivity Rogers ® RO3003 high-frequency organic substrate. Index Terms-Board-level clock distribution, GHz and low power clock distribution, multiprocessor computer system, radio-frequency (RF) clock distribution, system signal integrity.

show abstract

Characterization and modeling of clock skew with process variations

Cited by 55 publications

References 7 publications

Analytical bound for unwanted clock skew due to wire width variation

Analytical bound for unwanted clock skew due to wire width variation

Modeling and analysis of nonuniform substrate temperature effects on global ULSI interconnects

Over GHz low-power RF clock distribution for a multiprocessor digital system

Contact Info

Product

Resources

About