Modeling and analysis of nonuniform substrate temperature effects on global ULSI interconnects

Abstract

Non-uniform thermal profiles on the substrate in high-performance ICs can significantly impact the performance of global on-chip interconnects. This paper presents a detailed modeling and analysis of the interconnect performance degradation due to the non-uniform temperature profiles that are encountered along long metal interconnects as a result of existing thermal gradients in the underlying Silicon substrate.A non-uniform temperature-dependent distributed RC interconnect delay model is proposed. The model is applied to a wide variety of interconnect layouts and substrate temperature distributions to quantify the impact of such thermal non-uniformities on signal integrity issues including speed degradation in global interconnect lines and skew fluctuations in clock signal distribution networks. Subsequently, a new thermally dependent zero-skew clock routing methodology is presented. This study suggests that thermally-aware analysis should become an integrated part of the various optimization steps in physicalsynthesis flow to improve the performance and integrity of signals in global ULSI interconnects.

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