Triple-level metal process for high-performance and high-density 0.6-μm/5-V application-specific integrated circuits

Abstract

In this paper a triple level metal interconnect process for a coqimercially available high density, high performance 0.6 tm/5V CMOS technology is described. Polyates of 0.6 p.m (Leff 0.45 p.m) were fabricated and then planarized by BPSG reflow and resist etch back. Blanket W and etch back was used to fill high aspect ratio contacts and vias with TIN as the nucleation barrier. Low temperature RTA was performed after TiTFiN deposition, and RF etch was performed for contacts and vias respectively, prior to TiTfiN depositing, to achieve reliable contacts and via resistance. Stable contacts/via resistance down to 0.7 m with goodjunction integrity/stackability and negative metal enclosure has been demonstrated and been physically characterized by HTEM. TiN/AL-Cu/TiN was used for M1/M2/M3 interconnection and TEOS/ resist etch back /TEOS refill was used for lID 1 and ILD2. A TEOS/nitride sandwich was used for final passivation. A satisfactory yield has been achieved on 2.9 cm2 die size with 0.6 million usable gates.