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Band-gap engineering using SiGe channels to reduce the threshold voltage (V TH ) in p-channel MOSFETs has enabled a simplified gate-first high-κ/metal gate (HKMG) CMOS integration flow. Integrating Silicon-Germanium channels (cSiGe) on silicon wafers for SOC applications has unique challenges like the oxidation rate differential with silicon, defectivity and interface state density in the unoptimized state, and concerns with T inv scalability. In overcoming these challenges, we show that we can leverage the superior mobility, low threshold voltage and NBTI of cSiGe channels in high-performance (HP) and low power (LP) HKMG CMOS logic MOSFETs with multiple oxides utilizing dual channels for nFET and pFET.Introduction:

We improve the method proposed by Yao et al (2003) to resolve the X-ray dust scattering halos of point sources. Using this method we re-analyze the Cygnus X-1 data observed with Chandra (ObsID 1511) and derive the halo radial profile in different energy bands and the fractional halo intensity (FHI) askeV . We also apply the method to the Cygnus X-3 data (Chandra ObsID 425) and derive the halo radial profile from the first order data with the Chandra ACIS+HETG. It is found that the halo radial profile could be fit by the halo model MRN (Mathis, Rumpl & Nordsieck, 1977) and WD01 (Weingartner & Draine, 2001); the dust clouds should be located at between 1/2 to 1 of the distance to Cygnus X-1 and between 1/6 to 3/4 (from MRN model) or 1/6 to 2/3 (from WD01 model) of the distance to Cygnus X-3, respectively.

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We propose a plasma and thermal damagefie gate process named "Dmnascerae gate process" where CMP (Chemical Mechanical Polishmg) is used in forming gate structure. By uSbg this process, M y planarized high performance metal (W/TiN or MiN) gate transistors with pure SiO, or TazO5 as gate insulators were fabricated with very d o r m and highly reliable electrical characteristics. Therdore, this technology is usehl in fabricating 0.1 pm MOSFETs and beyond.

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Intrinsic correlation between mobility reduction by remote Coulomb scattering (RCS) and threshold voltage shift (ΔV t ), both of which are induced by interface dipole modulation at high-k/SiO 2 interface, is investigated. Three types of dipole modulation are examined; Al addition, La addition, and changing quality of interfacial SiO 2 layer. Extrinsic scattering components due to increases of interface state and surface roughness are extracted and separated. It is found that RCS due to interface dipole modulation by Al addition increases with increasing ΔV t , while that by La addition is constant, independent of ΔV t . Inevitability of additional scattering for ΔV t is discussed based on two different models for dipole formation mechanisms. IntroductionAggressive MOSFET device scaling requires a metal gate (MG)/high-k insulator (HK) gate stack [1] . Achieving suitable threshold voltage (V t ) for CMOS is one of the biggest issues for introduction of MG/HK stack, especially in production by gate-first process. Recently, the presence of energy offset at the high-k/SiO 2 interface is evidenced [2][3][4] , which is attributed to interfacial dipole layer. V t control technique by modulation of the interface dipole with adding atoms has been developed for CMOS integration. La [2,[5][6][7][8] and Al [3,4,9] are widely known to be effective for lowering V t of nMOS and pMOS, respectively. V t shift (ΔV t ) of several hundred mV due to interface dipole modulation corresponds to formation of charges (negative and positive) of larger than 10 13 cm -2 at the high-k/interfacial layer (IL) interface, which may affect channel mobility (μ) by remote Coulomb scattering (RCS) mechanism [10] . From observation of strong correlation between μ reduction and ΔV t , Ota et.al. [11] proposed a model that interface dipole scattering governs μ of high-k MOSFET. According to this model, tradeoff relation between μ reduction and ΔV t is inevitable. However, there are several reports showing an unaffected μ for V t shifted device [7,8] . It is of great importance to clarify intrinsic correlation between μ reduction and ΔV t after correcting μ reduction by extrinsic effects depending on processes.In this paper, we systematically investigate quantitative correlation between μ reduction and ΔV t . Three types of V t shifts are examined; Al addition, La addition, and changing quality of IL. Extrinsic scattering components by increases of interface state and surface roughness are experimentally