A thermally-stable sub-0.9nm EOT TaSix/HfSiON gate stack with high electron mobility, suitable for gate-first fabrciation of hp45 LOP devices

Dependences of Device Performances on Interfacial Layer Materials of High-k MISFETs due to Wave Function Penetration into Gate Dielectrics

“…Materials with low barrier heights and high dielectric constants can be promising candidates for interfacial layer of gate dielectrics with a thickness of less than 1 nm. 0.5 [8] 0.5 [9] 0.2 0.2 0.2 0.2 [9] 3.9 7.8 10 28 [4] 175 [5] 0.32 [9] 0.41 [9] 0.…”

Carbon-Free Tantalum-Nitride Film from Ammonia and Extremely Diluted Pentakis-dimethylamino-Tantalum; Effect of Silicon Incorporation to nMIS-FET Metal-Gate

“…High-k MIS-FETs were fabricated with a conventional gate-first process. The wire-metal was 50nm W. The gate dielectric was 2.5nm HfSiON giving an effective-oxide-thickness (EOT) of 1.1nm [2,3]. Activation temperatures after gate-formation were 850-1000 o C. TiN and TiSiN metal-gate transistors were fabricated with the same process.…”

Interfacial Reaction of TiN/HfSiON Gate Stack in High-Temperature Annealing for Gate-First Metal–Oxide–Semiconductor Field-Effect Transistors

“…Two conditions of postdeposition annealing (PDA) and nitridation of the HfSiO were set as follows. 15,16) One was that HfSiO postdeposition annealing (PDA) was performed at 700 C followed by nitridation by NH 3 annealing. Another was that plasma nitridation was performed followed by 1050 C postnitridation annealing (PNA).…”