Intrinsic correlation between mobility reduction and V<inf>t</inf> shift due to interface dipole modulation in HfSiON/SiO<inf>2</inf> stack by La or Al addition

Abstract

Intrinsic correlation between mobility reduction by remote Coulomb scattering (RCS) and threshold voltage shift (ΔV t ), both of which are induced by interface dipole modulation at high-k/SiO 2 interface, is investigated. Three types of dipole modulation are examined; Al addition, La addition, and changing quality of interfacial SiO 2 layer. Extrinsic scattering components due to increases of interface state and surface roughness are extracted and separated. It is found that RCS due to interface dipole modulation by Al addition increases with increasing ΔV t , while that by La addition is constant, independent of ΔV t . Inevitability of additional scattering for ΔV t is discussed based on two different models for dipole formation mechanisms. IntroductionAggressive MOSFET device scaling requires a metal gate (MG)/high-k insulator (HK) gate stack [1] . Achieving suitable threshold voltage (V t ) for CMOS is one of the biggest issues for introduction of MG/HK stack, especially in production by gate-first process. Recently, the presence of energy offset at the high-k/SiO 2 interface is evidenced [2][3][4] , which is attributed to interfacial dipole layer. V t control technique by modulation of the interface dipole with adding atoms has been developed for CMOS integration. La [2,[5][6][7][8] and Al [3,4,9] are widely known to be effective for lowering V t of nMOS and pMOS, respectively. V t shift (ΔV t ) of several hundred mV due to interface dipole modulation corresponds to formation of charges (negative and positive) of larger than 10 13 cm -2 at the high-k/interfacial layer (IL) interface, which may affect channel mobility (μ) by remote Coulomb scattering (RCS) mechanism [10] . From observation of strong correlation between μ reduction and ΔV t , Ota et.al. [11] proposed a model that interface dipole scattering governs μ of high-k MOSFET. According to this model, tradeoff relation between μ reduction and ΔV t is inevitable. However, there are several reports showing an unaffected μ for V t shifted device [7,8] . It is of great importance to clarify intrinsic correlation between μ reduction and ΔV t after correcting μ reduction by extrinsic effects depending on processes.In this paper, we systematically investigate quantitative correlation between μ reduction and ΔV t . Three types of V t shifts are examined; Al addition, La addition, and changing quality of IL. Extrinsic scattering components by increases of interface state and surface roughness are experimentally

Low-frequency noise behavior of La-doped HfSiON/metal gate nMOSFETs

“…Mobilityfluctuation noise is closely connected to mobility degradation phenomenon through identical scattering mechanism [11]. Tatsumura et al [12] and C. Y. Kang et al [4] have reported that in La-doped HfSiON/metal gate nMOSFETs, La-doping caused mobility degradation at low field conditions and it was attributed to remote Coulomb scattering by La-induced dipole at high-k/IL interface. Therefore, the additional mobilityfluctuation noise of submicron La-doped devices for V gt ≤ 0.1 V may be attributed to remote Coulomb scattering by the Lainduced dipole.…”

Gate contact materials in Si channel devices

“…However, this step also requires a balance between these benefi cial mechanisms and the diffusion of metal from the capping layers to the dielectrics/semiconductor interface, which would cause deleterious V t shifts and mobility degradation. 32 The rest of the gate-fi rst fl ow follows the conventional CMOS fl ow.…”

“…Next, the NMOS capping layer (typically La 2 O 3 ) is deposited and similarly patterned and wet-etched from the PMOS regions. 32 The metal nitride gate electrode and polysilicon top electrode are deposited, and the entire gate stack must be patterned to defi ne the active gates. The next critical step occurs during the junction activation, which exceeds temperatures of 1000°C.…”

Gate-last TiN/HfO2 band edge effective work functions using low-temperature anneals and selective cladding to control interface composition

“…10) generations, while a number of researchers have investigated the ability to set near band edge work functions for gate-first using selective capping layers such as La 2 O 3 for N-metaloxide-semiconductor (NMOS) 11 and Al 2 O 3 for P-metal-oxidesemiconductor (PMOS). 12 However, there are a number of issues to using this technique particularly for PMOS where an ideal capping layer that does not cause equivalent oxide thickness (EOT) and mobility degradation has been elusive. 12 Conversely, gate-last technologies have also been demonstrated for the 45 nm (Ref.…”

“…12 However, there are a number of issues to using this technique particularly for PMOS where an ideal capping layer that does not cause equivalent oxide thickness (EOT) and mobility degradation has been elusive. 12 Conversely, gate-last technologies have also been demonstrated for the 45 nm (Ref. 13) and 32 nm (Refs.…”