Duplex Doppler sonography is a useful procedure which helps in the diagnosis of patients with Budd-Chiari syndrome.

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Here, we present an analytical modeling of electron mobility in two dimensional electron gas (2DEG)-yielding MgZnO/ZnO heterostructures, to ascertain dominant scattering mechanisms and physical parameters responsible for one-order lower value of electron mobility in sputtering-grown heterostructure as compared to that in molecular beam epitaxy-grown heterostructure. This work extensively probes all scattering components and their physical parameters, such as dislocation density, impurity density, mole fraction, 2DEG density, correlation length and lateral size, for their respective effects on electron mobility of sputtered heterostructure. The results suggest that dislocation density and alloy disorder scattering are the most dominant sources responsible for reduced electron mobility. This work is extremely crucial for achieving high electron mobility by optimizing the material growth parameters to attain low dislocation density, impurity density and interface roughness, for the development of low-cost ZnO-based heterostructure field effect transistors.

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The effects of circuit-level stress on both inverter operation and MOSFET characteristics have been investigated. Individual MOSFETs, with gate oxide thicknesses of 3.2 nm and active dimensions of 25 p x 25 p, are connected in an inverter configuration off-wafer via a low-leakage switch matrix. Inverters are stressed with a ramped voltage stress (RVS) of various magnitudes to induce different degrees of gate oxide degradation. In addition, voltage transfer curves (VTCs) of degraded inverters are simulated using a new circuit model. At the transistor level, both the PMOSFET and NMOSFET show increased gate leakage current up to eight orders of magnitude, severely reduced on-currents and transconductances (gm), and large threshold voltage (V,) shies of 100 mV or more. Different trends in inverter performance are observed following positive and negative stress. However, regardless of the stress polarity, circuit-level stress results in inverter performance degradation, such as reduced output swing, switching point shifts, and increased risdfall times. After the largest positive RVS, the output voltage swing has decreased from 1.8 V fresh, to 1.54 V poststress. Much larger changes in the inverter voltage (V-t) time domain performance are observed. The minimum output low voltage is similar to that of the VTC, but the rise time increased significantly enough that the output voltage is only pulled up to 660 mV (VDD =