Y<sub>2</sub>O<sub>3</sub>-Based Crossbar Array for Analog and Neuromorphic Computation

Kumar, Sanjay; Kumbhar, Dhananjay D.; Park, Jun H.; Kamat, Rajanish K.; Dongale, Tukaram D.; Mukherjee, Shaibal

doi:10.1109/ted.2022.3227890

Cited by 19 publications

(10 citation statements)

References 35 publications

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“…Synaptic weights assigned to the devices can be strengthened or weakened by controlling the conditions of presynaptic spikes, mimicking the functions of learning and memory in the human brain. 30 When a presynaptic spike was applied to the gate terminal of the fabricated device, the EPSCs were clearly initiated when the width and amplitude of pulse spikes were adjusted from 1 to 5 V and from 10 to 50 μs, respectively, as demonstrated in Supporting Information Figure S5a. The increase in the amplitude and width of the pulse spike effectively promoted the accumulation of larger amounts of mobile ions in the EGI/channel interface, and hence, the EPSC showed gradual changes from 0.04 to 0.70 μA.…”

Section: Resultsmentioning

confidence: 97%

“…36 However, it was noticeable that the τ 2 of the fabricated device was examined to be significantly longer than those obtained from the previously reported EGTs. [29][30][31][32][33][34]36 Interestingly, although there were no marked variations in EPSC characteristics between two devices (Supporting Information Figure S5c), the device using 7%-doped LZO showed a significant difference in PPF characteristics from the device using 10%doped LZO. The maximum PPF index and τ 2 value were obtained to be 209% and 88 ms for the device using 7%-doped LZO, as shown in Supporting Information Figure S5d.…”

Section: Resultsmentioning

confidence: 99%

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Weighted-Sum Operation of Three-Terminal Synapse Transistors in Array Configuration Using Spin-Coated Li-Doped ZrO₂ Electrolyte Gate Insulator

Kim,

Kwon,

Seong

et al. 2023

ACS Appl. Mater. Interfaces

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Artificial synapses with ideal functionalities are essential in hardware neural networks to allow for energy-efficient analog computing. Electrolyte-gated transistors (EGTs) are promising candidates for artificial synaptic devices due to their low voltage operations supported by large specific capacitances of electrolyte gate insulators (EGIs). We investigated the synapse transistor employing an In–Ga–Zn–O channel and a Li-doped ZrO2 (LZO) EGI so as to improve the short-term plasticity (STP) and long-term potentiation (LTP). The LZO EGIs showed distinct differences in characteristics depending on the Li doping concentration, and we adopted the optimum doping concentration of 10%. Based on the strong electric double layer effect secured from the LZO, we successfully demonstrated excellent synaptic operations with gradual modulations of excitatory synaptic plasticity with variations in amplitude, width, and number of applied pulse spikes. The introduction of the LZO EGI was verified to improve typical short-term plasticity such as paired-pulse facilitation. Furthermore, by minutely controlling the pulse spike conditions, the conversion to LTP from STP was clearly accomplished while implementing the anti-Hebbian spike timing-dependent plasticity. Finally, the array configuration of synaptic devices, which is essential for realizing neuromorphic computing, was also demonstrated. In a 3 × 3 array architecture, the weighted-sum operation was well emulated to assign multilevels in seven states with the pulse width modulation scheme.

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Section: Resultsmentioning

confidence: 97%

Section: Resultsmentioning

confidence: 99%

Weighted-Sum Operation of Three-Terminal Synapse Transistors in Array Configuration Using Spin-Coated Li-Doped ZrO₂ Electrolyte Gate Insulator

Kim,

Kwon,

Seong

et al. 2023

ACS Appl. Mater. Interfaces

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“…Therefore, such kind of devices is useful for non-volatile memory applications 25 . On the other hand, analog-type switching devices show gradual increase or decrease in the current and such property can be employed to mimic various synaptic learning properties 26 www.nature.com/scientificreports/ both kinds of switching is not observed in these devices (Fig. 1h).…”

Section: Resultsmentioning

confidence: 99%

Unraveling the importance of fabrication parameters of copper oxide-based resistive switching memory devices by machine learning techniques

Patil

Kundale

Sutar

et al. 2023

Sci Rep

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In the present study, various statistical and machine learning (ML) techniques were used to understand how device fabrication parameters affect the performance of copper oxide-based resistive switching (RS) devices. In the present case, the data was collected from copper oxide RS devices-based research articles, published between 2008 to 2022. Initially, different patterns present in the data were analyzed by statistical techniques. Then, the classification and regression tree algorithm (CART) and decision tree (DT) ML algorithms were implemented to get the device fabrication guidelines for the continuous and categorical features of copper oxide-based RS devices, respectively. In the next step, the random forest algorithm was found to be suitable for the prediction of continuous-type features as compared to a linear model and artificial neural network (ANN). Moreover, the DT algorithm predicts the performance of categorical-type features very well. The feature importance score was calculated for each continuous and categorical feature by the gradient boosting (GB) algorithm. Finally, the suggested ML guidelines were employed to fabricate the copper oxide-based RS device and demonstrated its non-volatile memory properties. The results of ML algorithms and experimental devices are in good agreement with each other, suggesting the importance of ML techniques for understanding and optimizing memory devices.

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“…The detailed fabrication process of the Y 2 O 3 -based memristor via dual ion beam sputtering (DIBS) − and direct current (DC) magnetron sputtering systems is presented in Figure . To fabricate the Y 2 O 3 -based memristor, a Si (100) substrate is utilized, and before deploying the insulating layer (IL), the unintentionally formed native oxide layer is removed through Ar + plasma etching for 10–15 min by utilizing the assist ion source of the DIBS system .…”

Section: Memristor Fabrication and Characterizationsmentioning

confidence: 99%

Experimental Validation of Switching Dependence of Nanoscale Y₂O₃ Memristors on Electrode Symmetry via Physical Electrothermal Modeling

Gautam,

Kumar,

Chaudhary

et al. 2023

ACS Appl. Electron. Mater.

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In this work, the impact of symmetric and asymmetric electrodes on the resistive switching (RS) behavior of the nanoscale Y 2 O 3 -based memristor is investigated with experiments. In addition, the extracted switching parameters are validated with systemic modeling. Memristor growth is deployed by utilizing a dual ion beam sputtering (DIBS) system, and simulation is carried out in a semiconductor physicsbased tool, i.e., COMSOL Multiphysics with a defined MATLAB script. The performed simulation work is based on the minimum free energy of the used materials at an applied certain voltage. The simulated results exhibit a stable pinched hysteresis loop in the RS responses either in symmetric or asymmetric electrode combinations with an efficient ON/ OFF current ratio and show a close match with the experimental results. Moreover, the simulated devices show synaptic plasticity functionalities in terms of potentiation and depression processes with an almost ideal linearity factor for both electrode combinations similar to the realistic experimental data. Therefore, the present work efficiently depicts the suitability of the electrode material with the Y 2 O 3 switching layer to enhance electrical performance to integrate into the artificial synapse and neuromorphic computations.

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Y₂O₃-Based Crossbar Array for Analog and Neuromorphic Computation

Cited by 19 publications

References 35 publications

Weighted-Sum Operation of Three-Terminal Synapse Transistors in Array Configuration Using Spin-Coated Li-Doped ZrO₂ Electrolyte Gate Insulator

Weighted-Sum Operation of Three-Terminal Synapse Transistors in Array Configuration Using Spin-Coated Li-Doped ZrO₂ Electrolyte Gate Insulator

Unraveling the importance of fabrication parameters of copper oxide-based resistive switching memory devices by machine learning techniques

Experimental Validation of Switching Dependence of Nanoscale Y₂O₃ Memristors on Electrode Symmetry via Physical Electrothermal Modeling

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Y2O3-Based Crossbar Array for Analog and Neuromorphic Computation

Cited by 19 publications

References 35 publications

Weighted-Sum Operation of Three-Terminal Synapse Transistors in Array Configuration Using Spin-Coated Li-Doped ZrO2 Electrolyte Gate Insulator

Weighted-Sum Operation of Three-Terminal Synapse Transistors in Array Configuration Using Spin-Coated Li-Doped ZrO2 Electrolyte Gate Insulator

Unraveling the importance of fabrication parameters of copper oxide-based resistive switching memory devices by machine learning techniques

Experimental Validation of Switching Dependence of Nanoscale Y2O3 Memristors on Electrode Symmetry via Physical Electrothermal Modeling

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Product

Resources

About

Y₂O₃-Based Crossbar Array for Analog and Neuromorphic Computation

Weighted-Sum Operation of Three-Terminal Synapse Transistors in Array Configuration Using Spin-Coated Li-Doped ZrO₂ Electrolyte Gate Insulator

Weighted-Sum Operation of Three-Terminal Synapse Transistors in Array Configuration Using Spin-Coated Li-Doped ZrO₂ Electrolyte Gate Insulator

Experimental Validation of Switching Dependence of Nanoscale Y₂O₃ Memristors on Electrode Symmetry via Physical Electrothermal Modeling