Effects of circuit-level stress on inverter performance and MOSFET characteristics

Abstract

The effects of circuit-level stress on both inverter operation and MOSFET characteristics have been investigated. Individual MOSFETs, with gate oxide thicknesses of 3.2 nm and active dimensions of 25 p x 25 p, are connected in an inverter configuration off-wafer via a low-leakage switch matrix. Inverters are stressed with a ramped voltage stress (RVS) of various magnitudes to induce different degrees of gate oxide degradation. In addition, voltage transfer curves (VTCs) of degraded inverters are simulated using a new circuit model. At the transistor level, both the PMOSFET and NMOSFET show increased gate leakage current up to eight orders of magnitude, severely reduced on-currents and transconductances (gm), and large threshold voltage (V,) shies of 100 mV or more. Different trends in inverter performance are observed following positive and negative stress. However, regardless of the stress polarity, circuit-level stress results in inverter performance degradation, such as reduced output swing, switching point shifts, and increased risdfall times. After the largest positive RVS, the output voltage swing has decreased from 1.8 V fresh, to 1.54 V poststress. Much larger changes in the inverter voltage (V-t) time domain performance are observed. The minimum output low voltage is similar to that of the VTC, but the rise time increased significantly enough that the output voltage is only pulled up to 660 mV (VDD =

Degradation of Rise Time in NAND Gates Using 2.0 nm Gate Dielectrics

“…6) by 1 (i 3.6%), and a decrease in GmmA,4x (Fig. 6) by 24.2% (d 3 Additionally, a decrease in IOFF (Fig. 7) (Fig.…”

“…is decreasing with wearout, RcH will increase according to equation (3). Ultimately, less channel carriers are present and the effective channel resistance is greater in a device that has experienced wearout.…”

“…The NAND V-t response shows an increase in rise time (tr) ranging from 64.2% with a standard deviation of ±17.5% for configuration 1-3, and 62.7% with a standard deviation of ±20.2% for configuration 2-1. Previous work on inverter reliability by Stutzke et al shows the pMOSFET is the "pull-up" device, thereby affecting tr, while the nMOSFET is the "pull-down" device, which affects fall time (tf) [3]. Since only the pMOSFET experiences wearout, a change in tf is not expected nor is observed.…”

“…Inverter circuit degradation attributed to dielectric wearout or breakdown mechanisms have received recent attention [1][2][3][4][5][6][7][8], yet reports on physical (i.e., not simulated) oxide degradation effects on other logic gates, such as the NAND gate, are minimal. Furthermore, much of the work on inverter reliability has focused on the change of dc voltage transfer characteristics following circuit stressing without investigating the time domain [1,2,7,8].…”

“…In these studies, individual MOSFETs cannot be examined, so the type and amount of degradation to one or both MOSFETs can only be inferred. This is not the case with techniques (switch matrix techniques) developed by several of the authors of this paper in which individual MOSFETs in an inverter can be directly characterized following circuit stress [3,6]. The switch matrix technique has also been used to degrade a single MOSFET (or both MOSFETs) and examine the effect on inverter performance [9].…”