Investigation of circuit-level oxide degradation and its effect on CMOS inverter operation and MOSFET characteristics

Cheek, B.J.; Stutzke, N. A.; Kumar, Sanjay; Baker, R. Jacob; Moll, Amy; Knowlton, William B.

doi:10.1109/relphy.2004.1315309

Cited by 11 publications

(12 citation statements)

References 17 publications

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“…For digital CMOS circuitry, the soft breakdown phenomenon of gate oxide may cause slowdown of the circuit and increase of standby current, but usually not catastrophic failures of the transistor [21]- [23]. However, for the 3D-OTP memories, soft breakdown can be a problem for the reliable operation of the chip.…”

Section: Antifuse Breakdown Characteristicsmentioning

confidence: 99%

Evaluation of<tex>$hboxSiO_2$</tex>Antifuse in a 3D-OTP Memory

Yang

Meeks

et al. 2004

IEEE Trans. Device Mater. Relib.

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We have evaluated an antifuse technology used in a novel three-dimensional one-time-programmable (3D-OTP) nonvolatile solid-state memory. The 3D-OTP memory uses deposited polysilicon antifuse sandwiches to build its memory cells. The polysilicon based SiO 2 antifuse show different breakdown characteristics compared to conventional traditional gate oxides. Long-term storage tests show that this 3D-OTP solid-state memory not only can be a general purpose ROM, but also can be an ideal media for archiving.Index Terms-Antifuse, archival media, nonvolatile memory, oxide breakdown, 3D memory.

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Section: Antifuse Breakdown Characteristicsmentioning

confidence: 99%

Evaluation of<tex>$hboxSiO_2$</tex>Antifuse in a 3D-OTP Memory

Yang

Meeks

et al. 2004

IEEE Trans. Device Mater. Relib.

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“…The effects of dielectric breakdown mechanisms on inverter circuit performance have received recent attention [1][2][3][4][5][6][7][8], yet experimental results (i.e., not simulated) on these effects on other logic gates, such as the NAND gate, are negligible. Furthermore, the focus of reliability studies on the inverter logic circuit has involved the detrimental aspects of a circuit level stress on the DC voltage transfer characteristics (VTC) exclusive of circuit response in the time-domain [1,2,7,8].…”

Section: Introductionmentioning

confidence: 99%

Impact of single pMOSFET dielectric degradation on NAND circuit performance

Estrada

Ogas

Southwick

et al. 2008

Microelectronics Reliability

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Degradation of CMOS NAND logic circuits resulting from dielectric degradation of a single pMOSFET using constant voltage stress has been examined by means of a switch matrix technique. As a result, the NAND gate rise time increases by greater than 65%, which may lead to timing errors in high frequency digital circuits. In addition, the NAND gate DC switching point voltage shifts by nearly 11% which may be of consequence for analog or mixed signal applications. Experimental results for the degraded pMOSFET reveal a decrease in drive current by approximately 43%. There is also an increase in threshold voltage by 23%, a decrease in source to drain conductance of 30%, and an increase in channel resistance of about 44%. A linear relationship between the degradation of the pMOSFET channel resistance and the increase in NAND gate rise time is demonstrated, thereby providing experimental evidence of the impact of a single degraded pMOSFET on NAND circuit performance.

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“…Inverter circuit degradation attributed to dielectric wearout or breakdown mechanisms have received recent attention [1][2][3][4][5][6][7][8], yet reports on physical (i.e., not simulated) oxide degradation effects on other logic gates, such as the NAND gate, are minimal. Furthermore, much of the work on inverter reliability has focused on the change of dc voltage transfer characteristics following circuit stressing without investigating the time domain [1,2,7,8].…”

Section: Introductionmentioning

confidence: 99%

“…In these studies, individual MOSFETs cannot be examined, so the type and amount of degradation to one or both MOSFETs can only be inferred. This is not the case with techniques (switch matrix techniques) developed by several of the authors of this paper in which individual MOSFETs in an inverter can be directly characterized following circuit stress [3,6]. The switch matrix technique has also been used to degrade a single MOSFET (or both MOSFETs) and examine the effect on inverter performance [9].…”

Section: Introductionmentioning

confidence: 99%