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Texas Instruments, Dallas, TXThe use of deep-submicron CMOS processes allows for an unprecedented degree of scaling in digital circuitry, but complicates implementation and integration of traditional RF and analog circuits. The explosive growth of cellular radios makes it imperative to find digital architectural solutions to these integration problems. A fully-digital frequency synthesizer and GFSK transmitter for a single-chip Bluetooth radio is proposed in [1]. In this paper, a second generation of the digital radio processor (DRP) targeting GSM/EDGE cellular radios is presented. The alldigital PLL (ADPLL) phase-noise performance is significantly improved through architectural and circuit enhancements, and its wideband frequency modulation capability is extended to accommodate wide frequency deviations for EDGE. To complete the polar TX modulation path, a fully digital amplitude modulation circuit is added.At the heart of the ADPLL (Fig. 17.5.1) lies a digitally-controlled oscillator (DCO) [2]. The oscillator core (Fig. 17.5.2) operates at twice the 1.6 to 2.0GHz high-band frequency, which is then divided for precise generation of RX quadrature signals. The single DCO is shared between the TX and RX, and is used for both the high bands (HB) and the low bands (LB). Additional 4b of the tracking bank are dedicated for ∆Σ dithering in order to improve frequency resolution. The ADPLL sequencer traverses through the PVT calibration and acquisition modes during channel selection and frequency locking and stays in the tracking mode during the transmission or reception of a burst. To extend the DCO range to accommodate for voltage and temperature drifts, and to allow wide frequency modulation, the coarser-step acquisition bits are engaged by subtracting an equivalent number (generally fractional) of the tracking bank varactors. The acquisition/tracking varactor frequency step calibration is performed in the background with minimal overhead using dedicated hardware. All the varactors are realized as n-poly/n-well MOSCAP devices that operate in the flat regions of their C-V curves. The new varactors and the DCO core structure result in better phase noise than in [2], which is needed to meet the stricter GSM requirements.The ADPLL operates in the phase domain as follows: The variable phase of the ADPLL is digitally represented by a fixed-point concatenation of the DCO edge-transition count R V [k] and the normalized time-to-digital converter (TDC) output ε[k]. The TDC measures and quantizes the time differences between the frequency reference (FREF) and the DCO edges. The sampled differentiated variable phase is subtracted from the frequency command word (FCW) by the digital frequency detector. The frequency error f E [k] samples are accumulated to create the phase error φ E [k] samples, which are then filtered by a fourth-order IIR filter and normalized by a proportional loop attenuator α. A parallel feed with coefficient ρ adds an integrated term to create type-II loop characteristics, which suppresses the DCO flicker n...

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A new linearization scheme is proposed, which compensates for nonlinear distortions experienced in the amplitudemodulation path of a digital polar EDGE transmitter integrated in a 65-nm CMOS transceiver system-on-chip (SoC) based on the Digital RF Processor (DRP) technology. The measured amplitude and phase distortions are stored in lookup tables and used for predistortion without requiring inversion computations, thus achieving significant complexity reduction. Adaptive linear interpolation along with adaptive resolution enhancement provides the desired performance across power levels. With the presented scheme, the transmitter's measured performance significantly exceeds the EDGE specifications with an error vector magnitude (EVM) of typically 3% and a close-in modulated spectrum of −64 dB at a 400-kHz offset from the carrier frequency.

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Digital sigma-delta modulators are used extensively in CMOS wireless SoC designs to achieve high-resolution data conversion while controlling the quantization noise spectrum. This paper presents an implementation of a 90nm CMOS digital band-pass sigma-delta modulator (SDM), running at 900 MHz. Conventional sigma-delta structures required to achieve such noise shaping are hardware intensive and do not meet the timing requirements when synthesized in 90nm technology using a static CMOS implementation. In this work, we present an unrolled LA architecture to achieve the necessary rate of operation. Unrolling is achieved by running two loops at half the frequency, while maintaining algorithmic equivalency between the original and proposed structures. The proposed architecture meets timing requirements of 900 MHz across all PVT corners at the cost of increase in area. The operating frequency for most of the hardware is halved, resulting in a 20% power consumption reduction.