All-digital PLL and transmitter for mobile phones

Wallberg, J.; Rezeq, S.; Hung, Chih‐Ming; Eliezer, Oren; Vemulapalli, S.; Fernando, C.; Maggio, K.; Staszewski, R.; Barton, N.; Lee, Meng-Chang; Cruise, P.; Entezari, M.; Muhammad, K.; Leipold, Dirk

doi:10.1109/jssc.2005.857417

Cited by 549 publications

(231 citation statements)

References 16 publications

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“…FM demodulaton an ADPLL circuit was proposed [14]. For mobile phones applications ADPLL is developed [15]. ADPLL is used in high-speed clock generation [16], [17].…”

Section: Applications Of Adpllmentioning

confidence: 99%

ALL Digital Phase-Locked Loop (ADPLL): A Survey

Lata¹,

Kumar²

2013

IJFCC

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“…FM demodulaton an ADPLL circuit was proposed [14]. For mobile phones applications ADPLL is developed [15]. ADPLL is used in high-speed clock generation [16], [17].…”

Section: Applications Of Adpllmentioning

confidence: 99%

ALL Digital Phase-Locked Loop (ADPLL): A Survey

Lata¹,

Kumar²

2013

IJFCC

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“…1) T2D Converter: The T2D converter generates either an up or a down pulse signal depending upon whether the feedback signal is behind or ahead of the reference clock, respectively [14], [15], which after filtering through a digital loop filter drives the DCO towards lock. A one-bit T2D converter is chosen as it is enough to achieve a frequency synchronization between the reference and feedback clock.…”

Section: E Digital Pllmentioning

confidence: 99%

A 0.24-nJ/bit Super-Regenerative Pulsed UWB Receiver in 0.18-$\mu$m CMOS

Thoppay¹,

Dehollain

Green

et al. 2011

IEEE J. Solid-State Circuits

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Abstract-This paper describes a receiver system design for impulse-radio ultra-wideband (IR-UWB) that operates at two carrier frequencies-3.494 and 3.993 GHz-with a 10-Mbps data rate. To reduce the power consumption of the front-end amplifiers, a super-regenerative architecture is used. An integrated circuit, implemented in a CMOS 0.18-m technology and operating with a 1.5-V power supply, exhibits energy consumption of 0.24 nJ/bit with a measured sensitivity of 66 and 61 dBm at 3.494 and 3.993 GHz, respectively, with a BER of . Also included on the integrated circuit is an automatic tuning circuit based on a digital phase-locked loop that is used to set the resonant frequency of the super-regenerative block.Index Terms-Digital phase-locked loop, oscillator, receiver architecture, super-regenerative system, ultra-wideband communication, wireless sensor network.

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“…An example for the benefits of a structural test performed at the component level may be seen in the testing of a digitallycontrolled-oscillator (DCO) that has multiple banks of capacitors allowing it fine frequency resolution over a wide range, as described in [1]- [4].…”

Section: The Implementation Of Built-in Self-testing (Bist)mentioning

confidence: 99%

“…Several examples for built-in calibration/compensation may be found in [1]- [4], where parameters such as the DCO's modulation gain and the time-to-digital (TDC) step size are internally measured and calibration is realized digitally. Additional examples of similar nature may be found in [10]- [15], such as an oscillator's bias current that is adjusted to achieve optimal phase noise performance [10].…”

Section: Self-calibration/compensationmentioning

confidence: 99%

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Built-In Measurements in Low-Cost Digital-RF Transceivers

Eliezer

Staszewski

2011

IEICE Trans. Electron.

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SUMMARYDigital RF solutions have been shown to be advantageous in various design aspects, such as accurate modeling, design reuse, and scaling when migrating to the next CMOS process node. Consequently, the majority of new low-cost and feature cell phones are now based on this approach. However, another equally important aspect of this approach to wireless transceiver SoC design, which is instrumental in allowing fast and low-cost productization, is in creating the inherent capability to assess performance and allow for low-cost built-in calibration and compensation, as well as characterization and final-testing. These internal capabilities can often rely solely on the SoCs existing processing resources, representing a zero cost adder, requiring only the development of the appropriate algorithms. This paper presents various examples of built-in measurements that have been demonstrated in wireless transceivers offered by Texas Instruments in recent years, based on the digital-RF processor (DRP TM ) technology, and highlights the importance of the various types presented; built-in self-calibration and compensation, built-in self-characterization, and builtin self-testing (BiST). The accompanying statistical approach to the design and productization of such products is also discussed, and fundamental terms related with these, such as 'soft specifications', are defined. key words: system-on-chip (SoC), digital RF processor (DRP), design for testability (DfT), design for manufacturability (DfM), built-in self-testing (BiST), soft specifications

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All-digital PLL and transmitter for mobile phones

Cited by 549 publications

References 16 publications

ALL Digital Phase-Locked Loop (ADPLL): A Survey

ALL Digital Phase-Locked Loop (ADPLL): A Survey

A 0.24-nJ/bit Super-Regenerative Pulsed UWB Receiver in 0.18-$\mu$m CMOS

Built-In Measurements in Low-Cost Digital-RF Transceivers

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