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Electronic health records (EHRs) security is a critical challenge in the implementation and administration of Internet of Medical Things (IoMT) systems within the healthcare sector’s heterogeneous environment. As digital transformation continues to advance, ensuring privacy, integrity, and availability of EHRs become increasingly complex. Various imaging modalities, including PET, MRI, ultrasonography, CT, and X-ray imaging, play vital roles in medical diagnosis, allowing healthcare professionals to visualize and assess the internal structures, functions, and abnormalities within the human body. These diagnostic images are typically stored, shared, and processed for various purposes, including segmentation, feature selection, and image denoising. Cryptography techniques offer a promising solution for protecting sensitive medical image data during storage and transmission. Deep learning has the potential to revolutionize cryptography techniques for securing medical images. This paper explores the application of deep learning techniques in medical image cryptography, aiming to enhance the privacy and security of healthcare data. It investigates the use of deep learning models for image encryption, image resolution enhancement, detection and classification, encrypted compression, key generation, and end-to-end encryption. Finally, we provide insights into the current research challenges and promising directions for future research in the field of deep learning applications in medical image cryptography.

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An extension to a formal verification approach of hybrid systems is proposed to verify analog and mixed signal (AMS) designs. AMS designs can be formally modeled as hybrid systems and therefore lend themselves to the formal analysis and verification techniques applied to hybrid systems. The proposed approach employs simulation traces obtained from an actual design implementation of AMS circuit blocks (for example, in the form of SPICE netlists) to carry out formal analysis and verification. This enables the same platform used for formally validating an abstract model of an AMS design, to be also used for validating its different refinements and design implementation; thereby, providing a simple route to formal verification at different levels of implementation. The feasibility of the proposed approach is demonstrated with a case study based on a tunnel diode oscillator. Since the device characteristic of a tunnel diode is highly non-linear with a negative resistance region, dynamic behavior of circuits in which it is employed as an element is difficult to model, analyze and verify within a general hybrid system formal verification tool. In the case study presented the formal model and the proposed computational techniques have been incorporated into CheckMate, a formal verification tool based on MATLAB and Simulink-Stateflow Framework from MathWorks.

In semiconductor industry, reusability-based System-on-Chip architecture using hardware intellectual property (IP) cores play a prominent role in Internet-of-Things (IoT) applications for secure data transmission. The advent of IoT makes it possible for physical things to transmit, process, compute, and receive data over internet. But, it also introduces in-device communication security vulnerabilities. Advanced Encryption Standard (AES) IP has been used to address security vulnerabilities in IoT. It is an efficient and high-performance crypto algorithm used in IoT devices for secure and fast data encryption. However, due to rise of many attacks, the security of AES IP is also under threat. Hardware obfuscation is one such prominent countermeasure that mitigates hardware attacks such as tampering, reverse engineering, and malicious alteration. This article presents secure AES IP mechanism using the potential technique of obfuscation inspired by the concept of combinational hardware Trojan. Experimental results show that the proposed technique is resilient against reverse-engineering, malicious alteration, Boolean satisfiability attack, and key-sensitizing attacks. The confusion and diffusion features of obfuscated AES IP are higher in terms of Hamming distance, avalanche effect, and balance rate. The proposed technique is implemented in Basys-3 FPGAs within 5% of power and area overhead while maintaining high throughput.

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