Towards formal verification of analog mixed signal designs using SPICE circuit simulation traces

Abstract

An extension to a formal verification approach of hybrid systems is proposed to verify analog and mixed signal (AMS) designs. AMS designs can be formally modeled as hybrid systems and therefore lend themselves to the formal analysis and verification techniques applied to hybrid systems. The proposed approach employs simulation traces obtained from an actual design implementation of AMS circuit blocks (for example, in the form of SPICE netlists) to carry out formal analysis and verification. This enables the same platform used for formally validating an abstract model of an AMS design, to be also used for validating its different refinements and design implementation; thereby, providing a simple route to formal verification at different levels of implementation. The feasibility of the proposed approach is demonstrated with a case study based on a tunnel diode oscillator. Since the device characteristic of a tunnel diode is highly non-linear with a negative resistance region, dynamic behavior of circuits in which it is employed as an element is difficult to model, analyze and verify within a general hybrid system formal verification tool. In the case study presented the formal model and the proposed computational techniques have been incorporated into CheckMate, a formal verification tool based on MATLAB and Simulink-Stateflow Framework from MathWorks.

SFV: A Scalable Approach to Formal Verification for AMS SoC

“…The proposed approach completes the verification work on the tunnel diode oscillator in 10.39s, and outperforms model checker HyTech which consumes 68.4 s. This indicates that our method can provide drastic performance improvement over two other methods with no loss in verification accuracy. Table 1 shows the verification results for HyTech [10], LHPN [11] and the proposed method. The same parameters as…”

“…HyTech [10] LHPN [11] Proposed The proposed verification method mainly deals with modeling for oscillating behavior and non-oscillating behaviors of tunnel diode oscillator using 32-bit discrete regions. When R=200Ω, LHPN model uses 13.01 s for property verification.…”

“…We failed to use tool HyTech for verification because of overflow errors. HyTech model checking accomplishes oscillating property checking for tunnel diode oscillator within 68.4 s, however the proposed method only takes 11.57 s, hence obtains higher efficiency than that in [11]. Table 2 shows the verification results comparisons among the proposed method, PHAVer [13] and LEMA [10].…”

A New Verification Method of Digital Circuits Based on Cone-Oriented Partitioning and Decision Diagrams

“…For the verification of analog and mixed signal systems, K. Lata [6] studied the formal verification approach of hybrid systems, used simulation traces obtained from an actual design implementation of analog and mixed signal circuit blocks to carry out formal analysis and verification. D. Walter [7] studied the symbolic model checking algorithms for the verification of analog/mixed-signal circuits, the algorithms were based on binary decision diagrams and a bounded model checker that uses a satisfiability modulo theory solver.…”