ALL Digital Phase-Locked Loop (ADPLL): A Survey

Lata, Kusum; Kumar, Manoj

doi:10.7763/ijfcc.2013.v2.225

Cited by 18 publications

(5 citation statements)

References 13 publications

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“…In other words, ADPLL is a fully digital version of a phase-locked loop (PLL) [16]. It consists of three components: phase detectors (PD), loop filters (LF), and digital control oscillators (DCO) [17]. The three units are connected in a closed-loop feedback system.…”

Section: Detail Description About Adpll For Trng Architecture Impleme...mentioning

confidence: 99%

“…The input phase ν1, output phase ν2, and frequency are all interlocked using ADPLL. PD is used to reduce the gap between the two signals used in ADPLL [17].…”

Section: Digital Phase Detectormentioning

confidence: 99%

“…DCO is a modified oscillator that modulates the frequency of a signal using the loop-filter output [17]. They adjust their frequency depending on the loop filter's output.…”

Section: Adpll's Digital Control Oscillator (Dco)mentioning

confidence: 99%

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FPGA implantations of TRNG architecture using ADPLL based on FIR filter as a loop filter

Meitei

Kumar

2022

SN Appl. Sci.

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This article describes about the design, implementation, and analysis of a true random number generator (TRNG) employing an all-digital phase-locked loop (ADPLL) based on a finite impulse response (FIR) filter as the digital loop filter and implemented on the Artix 7(XC7A35T-CPG236-1) field programmable gate array (FPGA) board using the Xilinx Vivado v.2015.2 design suite. The coefficients of a 3rd-order broadcast low-pass digital FIR filter are computed using the Keiser window method. The MATLAB-FDA tool is used to calculate the filter coefficient. After reducing the bias in the sequence using the XOR-corrector post-processing approach, the suggested ADPLL-based TRNG designs created an unbiased stochastic random number with an overall throughput of 200 Mbps for both designs. The first proposed FIR-ADPLL-based TRNG design (FAT-1) consumes 0.072 W of power, whereas the second proposed FIR-ADPLL-based TRNG design (FAT-2) consumes 0.074 W. The resulting bitstream is verified for randomness using national institute of standards and technology (NIST) test following post-processing. Digital storage oscilloscope (DSO) is interfaced to the Artrix-7 FPGA board in order to capture the TRNG output waveforms. Both the proposed FIR-based ADPLL-TRNG designs passed the NIST SP 800-22 test, indicating that they are well-suited for a variety of industrial applications, including network security, cybersecurity, banking security, smart cards, radio-frequency identification tags, Internet of Things, and Industrial Internet of Things.

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Section: Detail Description About Adpll For Trng Architecture Impleme...mentioning

confidence: 99%

“…The input phase ν1, output phase ν2, and frequency are all interlocked using ADPLL. PD is used to reduce the gap between the two signals used in ADPLL [17].…”

Section: Digital Phase Detectormentioning

confidence: 99%

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FPGA implantations of TRNG architecture using ADPLL based on FIR filter as a loop filter

Meitei

Kumar

2022

SN Appl. Sci.

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“…Software PLL (SPLL). [1] The analog PLL has high power consumption and large area. That makes the PLL's are noise sensitive and some are expensive.…”

Section: Introductionmentioning

confidence: 99%

A High Performance Kinetic Gas Molecule Optimization (KGMO) Based ADPLL for Induction Motors Control Applications

Dwibedi,

Logashanmugam*

2020

IJITEE

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Nowadays control applications play a major role in different applications such as industrial automation, robotics, automobiles, power systems etc. The all-digital phase-locked loop (ADPLL) is a digital controller can be used commonly for all kind of control applications based on the application requirement. In the work, KGMO based ADPLL is proposed to perform the rotation control of an induction motor (KGMO-ADPLL-IMSC) under various load conditions by the varying current. The proposed ADPLL is tested in an induction motor (IM) to control the rotation of the motor under certain load conditions. Various parameters such as speed, torque, phase, amplitude and offset values are considered to generate the control signal. Root mean square error (RMSE) is considered as the objective function for the KGMO algorithm. Least error is considered for the best fitness function for the better performance. In this work, the current control technique is used to perform the rotation control of the induction motor. Various performance such as torque, speed and stability are measured under various load conditions. KGMO-ADPLL-IMSC design is implemented in an integrated MATLAB/SIMULINK environment under various inbuild and custom libraries. Experiments show that the KGMO-ADPLL-IMSC strategy is altogether improved the performance in terms of all performance evaluation graphs

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“…It generated clock signal ranges from 61MHZ to 325MHZ [2]. [4]. Prince Nuna G.K. and Urkar presented circuit in which PLL played main role.…”

Section: Introductionmentioning

confidence: 99%

Optimization of frequency settling time of PLL using 3rd MASH Sigma Delta Modulator

Patel*,

Das,

Sinha

2020

IJITEE

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To reduce settling time of PLL, an attempt to optimize the parameters has been proposed in this paper. The transient responses of various Phase Locked Loop (PLL) frequency synthesizer have been comparied with their active and passive poles effect. These results are presented on a type-II 3rd order PLL frequency synthesizer employing a 3rd order MASH sigma delta modulator. The simulation results show the improved performance of the fractional frequency synthesizer for the communication system. These results have been simulated using Advanced Design System(ADS) tool.

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ALL Digital Phase-Locked Loop (ADPLL): A Survey

Cited by 18 publications

References 13 publications

FPGA implantations of TRNG architecture using ADPLL based on FIR filter as a loop filter

FPGA implantations of TRNG architecture using ADPLL based on FIR filter as a loop filter

A High Performance Kinetic Gas Molecule Optimization (KGMO) Based ADPLL for Induction Motors Control Applications

Optimization of frequency settling time of PLL using 3rd MASH Sigma Delta Modulator

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