FPGA implantations of TRNG architecture using ADPLL based on FIR filter as a loop filter

Meitei, Huirem Bharat; Kumar, Manoj

doi:10.1007/s42452-022-04981-6

Cited by 6 publications

(5 citation statements)

References 32 publications

(30 reference statements)

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“…After wavelet transform, the valuable signal's energy is focused on some wavelet coefficients with large amplitude. According to this principle, we can set a threshold to reduce or even set the wavelet coefficients smaller than this reading value to zero, which will attenuate the wavelet coefficients corresponding to noise, thus achieving the purpose of noise elimination [8].…”

Section: Best Uniform Approximation Methodmentioning

confidence: 99%

Comparison and analysis of different ECG denoising methods

Zhou

2023

J. Phys.: Conf. Ser.

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With the improvement of medical level, electrocardiogram (ECG) is widely used for disease diagnosis. A lot of pathological and physiological information is contained in the ECG, which can be used to record the point activity of normal human heart and diagnose various heart disease. However, the acquired ECG signals are always contaminated with noise which caused by acquisition equipment or other circumstance. Therefore, Efficient denoising method is very important. In this paper, three typical ECG signal denoising methods are listed, including FIR filtering, wavelet filtering and EMD filtering. In this paper, the principles of the three filtering methods are introduced in detail, and their effects are compared. By comparison, it intuitively shows the processing effects of each method on ECG signals. Meanwhile, a simple Butterworth filter is designed to denoise a standard wave, which represents the logic knowledge related to denoising. It is very significant for the medical signal processing field and help to research more effective signal processing methods.

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Section: Best Uniform Approximation Methodmentioning

confidence: 99%

Comparison and analysis of different ECG denoising methods

Zhou

2023

J. Phys.: Conf. Ser.

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“…Figure 3. First-order ADPLL circuit diagram [10] The basic architecture of the ADPPL-based TRNG used in our proposed design is depicted in Figure 4. The existing TRNG using two identically design RO is very challenging to match the period while implementing in FPGA.…”

Section: Fpga Realization Of the Proposed Wireless Communication Netw...mentioning

confidence: 99%

“…Figure 5. DSO waveform of TRNG used in RIAT-WCS architecture [10] The test was carried out using an Artrix-7 FPGA system and the resulting pattern is captured using a digital storage oscilloscope. The FPGA pinouts for the TRNG implementation centered on ADPLL with Esp8266 for IoT application are listed in Tables 1 and 2.…”

Section: Fpga Realization Of the Proposed Wireless Communication Netw...mentioning

confidence: 99%

“…This article describes the layout, development, and interpretation of a design for true random number generators that employed the jitters created by an ADPLL centered on an finite impulse response (FIR) filter [10] as a digital low pass filter and the jitters obtained from the suggested ring oscillators as randomness sources. Ansari et al [11] TRNG-generated random numbers can be used to create highly secure cryptographic keys for the transmission and receipt of data in IoT devices.…”

Section: Introductionmentioning

confidence: 99%

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Implementation of a secure wireless communication system using true random number generator for internet of things

Meitei

Kumar

2023

IJEECS

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This paper describes the design and implementation of an internet of thing (IoT)-based application that uses a true random number generator (TRNG) with an all digital phase locked loop (ADPLL) for secure wireless communication. Field programmable gate array (FPGA) boards were used on the transmitter and receiver sides and were interfaced with Esp8266 chips to wirelessly send and receive encrypted sensor data. The MQ-2 gas sensor and tracking sensor were connected to the FPGA board on the transmitter side, where data from the sensors was encrypted using the exclusive-OR (XOR) function and the TRNG architecture. The system can be controlled by users through a web browser served by the ThingSpeak cloud. The Artix-7 FPGA device is used to implement the proposed wireless communication system, for which design and synthesis were done using the Xilinx Vivado 2015.2 tool. The proposed system uses a low amount of power and is suitable for a standalone, highly secure TRNG-based IoT application. The National Institute of Standard and Testing (NIST SP 800-22) test showed that ADPLL with finite impulse response (FIR) filter-based TRNGs are better for encrypting IoT devices for secure wireless communication.

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“…The commonly used method is to output the clock pulse by building a ring oscillator structure at present, but its disadvantage is that the duty cycle of the output clock pulse is not 50%, and there is jitter on the transition edge [10,11]. Although there are glitches in the output signal due to the existence of jitter in the circuit, which may affect the function of the circuit, the closed-loop phase adjustment circuit using a phase-locked loop ensures that the circuit can still output pulses stably in the presence of jitter [12]. In this paper, multi-phase sampling is performed on the dither circuit by generating sampling clocks of different phases through the PLL, which greatly improves the probability of sampling the dither and ensures the output of random sequences.…”

Section: Jitter Extraction Randomness Modelmentioning

confidence: 99%

A Low-overhead M_TRNG for Cryptographic Protection using Multiphase Sampling

Yao

Liang

2022

Preprint

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True Random Number Generator (TRNG) is built on hardware-based non-deterministic noise for generating keys, initialization vectors, and random numbers, and it plays an important role in various applications that require encryption protection.In this paper, a true random number generator based on MUX unit multi-phase sampling is proposed by studying the frequency jitter mechanism. The scheme is based on the "soft macro" design of the MUX unit, which replaces the traditional look-up table entropy scheme. It completes high-precision jitter sampling on the basis of ensuring the fairness of the TRNG entropy source, and can be well transplanted to a series of FPGAs. The proposed TRNG is verified on three FPGAs of Xilinx Virtex-6, Artix-7 and Virtex-7. The experimental results show that the generated random sequences are of good quality, passing the NIST SP800- 22 tests with higher p-value and NIST SP 800-90B tests with higher minimum entropy, while achieving 100Mbps throughput. It is worth mentioning that the resource overhead consumed by the proposed TRNG is small and unitary, only consuming 4 MUX units, 4 DFFs and 1 LUT unit, which has a good application prospect.

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FPGA implantations of TRNG architecture using ADPLL based on FIR filter as a loop filter

Cited by 6 publications

References 32 publications

Comparison and analysis of different ECG denoising methods

Comparison and analysis of different ECG denoising methods

Implementation of a secure wireless communication system using true random number generator for internet of things

A Low-overhead M_TRNG for Cryptographic Protection using Multiphase Sampling

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