A 24mm<sup>2</sup> Quad-Band Single-Chip GSM Radio with Transmitter Calibration in 90nm Digital CMOS

Leipold, Dirk; Eliezer, Oren; Entezari, M.; Muhammad, K.; Bashir, Imran; Hung, Chih‐Ming; Wallberg, J.; Staszewski, R.; Cruise, P.; Rezeq, S.; Vemulapalli, S.; Waheed, K.; Barton, N.; Lee, M.-C.; Fernando, C.; Maggio, K.; Jung, T.; Elahi, I.; Larson, Shawn D.; Murphy, Tom; Feygin, G.; Deng, I.; Mayhugh, T.; Ho, Yo-Chuol; Low, Kah-Mun; Lin, C.; Jaehnig, J.; Kerr, J.; Mehta, Jaimin; Glock, Stefan; Almholt, T.; Bhatara, S.

doi:10.1109/isscc.2008.4523130

Cited by 46 publications

(16 citation statements)

References 4 publications

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“…References [3], [22], [23] and [24] describe implementations of the ADPLL-based commercial RF-SoC's for Bluetooth (130 nm CMOS), GSM (90 nm CMOS) and EDGE (65 nm CMOS) wireless standards, respectively. ADPLL implementations also include Refs.…”

Section: Figmentioning

confidence: 99%

All-Digital RF Phase-Locked Loops Exploiting Phase Prediction

Zhuang

Staszewski

2014

IPSJ Transactions on System LSI Design Methodology

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This paper presents an all-digital phase-locked loop (ADPLL) architecture in a new light that allows it to significantly save power through complexity reduction of its phase locking and detection mechanisms. The predictive nature of the ADPLL to estimate next edge occurrence of the reference clock is exploited here to reduce the timing range and thus complexity of the fractional part of the phase detection mechanism as implemented by a time-to-digital converter (TDC) and to ease the clock retiming circuit. In addition, the integer part, which counts the DCO clock edges, can be disabled to save power once the loop has achieved lock. It can be widely used in fields of fractional-N frequency multiplication and frequency/phase modulation. The presented principles and techniques have been validated through extensive behavioral simulations as well as fabricated IC chips.

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Section: Figmentioning

confidence: 99%

All-Digital RF Phase-Locked Loops Exploiting Phase Prediction

Zhuang

Staszewski

2014

IPSJ Transactions on System LSI Design Methodology

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“…For such SoCs, implementation of calibration methods for RF/analog circuits becomes mandatory to overcome their performance degradation caused by process, voltage and temperature variations [2]. To minimize the energy consumption in transceivers, the calibration sequence should be accelerated by providing the predetermined calibration data from a nonvolatile memory (NV-M).…”

Section: Introductionmentioning

confidence: 99%

A 32-bit 16-program-cycle nonvolatile memory for analog circuit calibration in a standard 0.18µm CMOS

Lee

Masui

2012

IEICE Electron. Express

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Abstract:We propose a 32-bit 16-program-cycle nonvolatile memory fabricated in a standard 0.18 µm CMOS technology based on a channel hot-electron trapping at the transistor gate sidewall. Its target application is calibration of RF/analog circuits for multiband/multimode communication systems, that demands in-field multiple-time programmability and data select-ability. The issue of the one-time programmability in the proposed memory cell is overcome by the addressing memory cell array, and the promised reliability is observed through the optimization of program and restore operations. The developed nonvolatile memory is applied to a dual-band PLL synthesizer with an area overhead of 8.5%.

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“…Therefore, previous works have aimed at calibrating/compensating these nonlinearities. For the AM path, [7] utilizes the on-chip receiver to conduct the adaptive digital linearization of the DPA, whereas in [8] this is achieved by coupling the RF signal to the reference clock of the ADPLL. For the PM path, [9] proposes a least-mean square based gain calibration technique of the DCO.…”

Section: Introductionmentioning

confidence: 99%

RF BIST for ADPLL-based polar transmitters with wide-band DCO gain calibration

Yin

2011

2011 12th International Symposium on Quality Electronic Design

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We propose a BIST scheme to provide online testing for all-digital PLL based polar transmitters. Multiple digital signatures are collected by adding a branch digital filter optimized to increase the sensitivities to nonidealities. The test signatures are processed using simple digital processing to provide an estimate for error vector magnitude (EVM), a key RF performance measure for the transmitter. Additionally, a digital self-calibration scheme is proposed to eliminate the EVM degradation due to large wide-band DCO gain mismatch. We show that a proper exploration of digital implementation style is instrumental for facilitating novel low-cost built-in test and calibration solutions for mixed-signal and RF applications.

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A 24mm² Quad-Band Single-Chip GSM Radio with Transmitter Calibration in 90nm Digital CMOS

Cited by 46 publications

References 4 publications

All-Digital RF Phase-Locked Loops Exploiting Phase Prediction

All-Digital RF Phase-Locked Loops Exploiting Phase Prediction

A 32-bit 16-program-cycle nonvolatile memory for analog circuit calibration in a standard 0.18µm CMOS

RF BIST for ADPLL-based polar transmitters with wide-band DCO gain calibration

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A 24mm2 Quad-Band Single-Chip GSM Radio with Transmitter Calibration in 90nm Digital CMOS

Cited by 46 publications

References 4 publications

All-Digital RF Phase-Locked Loops Exploiting Phase Prediction

All-Digital RF Phase-Locked Loops Exploiting Phase Prediction

A 32-bit 16-program-cycle nonvolatile memory for analog circuit calibration in a standard 0.18µm CMOS

RF BIST for ADPLL-based polar transmitters with wide-band DCO gain calibration

Contact Info

Product

Resources

About

A 24mm² Quad-Band Single-Chip GSM Radio with Transmitter Calibration in 90nm Digital CMOS