A 0.8mm&lt;sup&gt;2&lt;/sup&gt; all-digital SAW-less polar transmitter in 65nm EDGE SoC

Mehta, Jaimin; Staszewski, Robert Bogdan; Eliezer, Oren; Rezeq, S.; Waheed, K.; Entezari, M.; Feygin, G.; Vemulapalli, S.; Zoicas, Vasile; Hung, Chih‐Ming; Barton, N.; Bashir, Imran; Maggio, K.; Fréchette, M.F.; Lee, Meng-Chang; Wallberg, J.; Cruise, P.; Yanduru, N.K.

doi:10.1109/isscc.2010.5434050

Cited by 35 publications

(33 citation statements)

References 3 publications

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“…References [3], [22], [23] and [24] describe implementations of the ADPLL-based commercial RF-SoC's for Bluetooth (130 nm CMOS), GSM (90 nm CMOS) and EDGE (65 nm CMOS) wireless standards, respectively. ADPLL implementations also include Refs.…”

Section: Figmentioning

confidence: 99%

All-Digital RF Phase-Locked Loops Exploiting Phase Prediction

Zhuang

Staszewski

2014

IPSJ Transactions on System LSI Design Methodology

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This paper presents an all-digital phase-locked loop (ADPLL) architecture in a new light that allows it to significantly save power through complexity reduction of its phase locking and detection mechanisms. The predictive nature of the ADPLL to estimate next edge occurrence of the reference clock is exploited here to reduce the timing range and thus complexity of the fractional part of the phase detection mechanism as implemented by a time-to-digital converter (TDC) and to ease the clock retiming circuit. In addition, the integer part, which counts the DCO clock edges, can be disabled to save power once the loop has achieved lock. It can be widely used in fields of fractional-N frequency multiplication and frequency/phase modulation. The presented principles and techniques have been validated through extensive behavioral simulations as well as fabricated IC chips.

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Section: Figmentioning

confidence: 99%

All-Digital RF Phase-Locked Loops Exploiting Phase Prediction

Zhuang

Staszewski

2014

IPSJ Transactions on System LSI Design Methodology

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“…The variation of the frequency is only possible through the creation of the variable quadratic current at the output of the tank, as shown by (2). A suitable topology to solve this problem should create a negative feedback to counterbalance the current .…”

Section: E Cancellation Of the Reactive Power Effectmentioning

confidence: 99%

“…Thus, adjacent carriers can spread over each other, resulting in inter-carrier interference [1]. Moreover, in order to limit the out-of-band noise, stringent high-frequency offset phase noise is also required [2].…”

Section: Introductionmentioning

confidence: 99%

Reactive Power Imbalances in LC VCOs and Their Influence on Phase-Noise Mechanisms

Koukab

2011

IEEE Trans. Microwave Theory Techn.

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Abstract-Phase-noise mechanisms in cross-coupled LC voltagecontrolled oscillators (VCOs) are reviewed based on a physical understanding of reactive power imbalances in the tank and in the active part. These phenomena are proven to be the predominant phase-noise degradation mechanism in relatively low-and highcurrent operations. Based on this analysis, a technique to suppress these detrimental effects is developed and implemented in an LC VCO design. The measured results confirm the dependencies predicted by the analysis, and the usefulness of the proposed technique to simultaneously optimize the phase noise at high and low offset frequencies. The measured VCO tuning range is 600 MHz, ranging from 2.4 to 3 GHz. The VCO-prescaler circuit exhibits a phase noise from 88 to 92 dBc/Hz at 15 kHz and from 155 to 160 dBc/Hz at 10 MHz, when the power consumption is 6 and 10 mA for the VCO and 2 mA for the prescaler, and the power supply is 2 V.Index Terms-Flicker noise, phase noise, power supply rejection (PSR), thermal noise, voltage-controlled oscillator (VCO).

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“…The presented Digital RF Processor (DRP)-based GSM/EDGE compliant transceiver integrated with the digital baseband was first disclosed in [2]. The polar EDGE transmitter consists of a digitally controlled oscillator (DCO)-based all-digital phase-locked loop (ADPLL) for the J.…”

Section: Introductionmentioning

confidence: 99%

Self-calibration of a power pre-amplifier in a digital polar transmitter

Mehta

Bashir

Zoicas

et al. 2010

2010 IEEE Dallas Circuits and Systems Workshop

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A built-in self-calibration and self-compensation scheme for a digital power pre-amplifier (DPA) of a mobile handset transceiver is proposed. It allows accurate internal measurements of the amplitude and phase distortions experienced in the DPA using the on-chip receiver and processor. A dynamic range of over 60 dB is achieved using multiple gain settings in the receiver. The proposed scheme, in conjunction with the transceiver's digital architecture, is demonstrated in a 65-nm CMOS GSM/EDGE radio, where it allows for accurate and cost-effective self-calibration to be performed in less than 0.1 s.

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A 0.8mm<sup>2</sup> all-digital SAW-less polar transmitter in 65nm EDGE SoC

Cited by 35 publications

References 3 publications

All-Digital RF Phase-Locked Loops Exploiting Phase Prediction

All-Digital RF Phase-Locked Loops Exploiting Phase Prediction

Reactive Power Imbalances in LC VCOs and Their Influence on Phase-Noise Mechanisms

Self-calibration of a power pre-amplifier in a digital polar transmitter

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