All-digital PLL and GSM/edge transmitter in 90nm CMOS

Abstract

Texas Instruments, Dallas, TXThe use of deep-submicron CMOS processes allows for an unprecedented degree of scaling in digital circuitry, but complicates implementation and integration of traditional RF and analog circuits. The explosive growth of cellular radios makes it imperative to find digital architectural solutions to these integration problems. A fully-digital frequency synthesizer and GFSK transmitter for a single-chip Bluetooth radio is proposed in [1]. In this paper, a second generation of the digital radio processor (DRP) targeting GSM/EDGE cellular radios is presented. The alldigital PLL (ADPLL) phase-noise performance is significantly improved through architectural and circuit enhancements, and its wideband frequency modulation capability is extended to accommodate wide frequency deviations for EDGE. To complete the polar TX modulation path, a fully digital amplitude modulation circuit is added.At the heart of the ADPLL (Fig. 17.5.1) lies a digitally-controlled oscillator (DCO) [2]. The oscillator core (Fig. 17.5.2) operates at twice the 1.6 to 2.0GHz high-band frequency, which is then divided for precise generation of RX quadrature signals. The single DCO is shared between the TX and RX, and is used for both the high bands (HB) and the low bands (LB). Additional 4b of the tracking bank are dedicated for ∆Σ dithering in order to improve frequency resolution. The ADPLL sequencer traverses through the PVT calibration and acquisition modes during channel selection and frequency locking and stays in the tracking mode during the transmission or reception of a burst. To extend the DCO range to accommodate for voltage and temperature drifts, and to allow wide frequency modulation, the coarser-step acquisition bits are engaged by subtracting an equivalent number (generally fractional) of the tracking bank varactors. The acquisition/tracking varactor frequency step calibration is performed in the background with minimal overhead using dedicated hardware. All the varactors are realized as n-poly/n-well MOSCAP devices that operate in the flat regions of their C-V curves. The new varactors and the DCO core structure result in better phase noise than in [2], which is needed to meet the stricter GSM requirements.The ADPLL operates in the phase domain as follows: The variable phase of the ADPLL is digitally represented by a fixed-point concatenation of the DCO edge-transition count R V [k] and the normalized time-to-digital converter (TDC) output ε[k]. The TDC measures and quantizes the time differences between the frequency reference (FREF) and the DCO edges. The sampled differentiated variable phase is subtracted from the frequency command word (FCW) by the digital frequency detector. The frequency error f E [k] samples are accumulated to create the phase error φ E [k] samples, which are then filtered by a fourth-order IIR filter and normalized by a proportional loop attenuator α. A parallel feed with coefficient ρ adds an integrated term to create type-II loop characteristics, which suppresses the DCO flicker n...

A fully integrated 24-GHz phased-array transmitter in CMOS

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A Low-Power Digitally Controlled Oscillator for All Digital Phase-Locked Loops

“…The functionality and performance are verified through a novel ADPLL that uses the proposed DCO. Usually the ADPLL structure based on the second order negative feedback system has a faster lock-in time with a limited lock-in range [11,12]. One the other hand, by separating the locking process into frequency and phase acquisition, a wide lock-in range is available [13,14].…”