A Low-Power Digitally Controlled Oscillator for All Digital Phase-Locked Loops

Zhao, Jun; Kim, Yong-Bin

doi:10.1155/2010/946710

Cited by 17 publications

(11 citation statements)

References 17 publications

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“…Figure 4 shows conventional and recently reported Schmitt triggers. A Schmitt trigger was introduced in [22] and has a conventional design that was used in [28,29] with four serial MOS transistors from supply to ground. Another low-power Schmitt trigger is illustrated in [22].…”

Section: Schmitt Trigger In Dcomentioning

confidence: 99%

“…The designs in [28,29] have good resolution, but the inter-stage delay utilizes more short circuit power by stepper slopes in the input stages of CMOS. The nonlinearity in higher code words is still a problem.…”

mentioning

confidence: 99%

“…The nonlinearity in higher code words is still a problem. However, a good idea was used in [28,29] to preserve the linearity in higher code words. They used a chain of tristate buffers in front of a multiplexor to select different delay paths to overcome the nonlinearity.…”

mentioning

confidence: 99%

“…It gains linearity at the cost of more power. The designs in [16,28,29] are our inspirational start point. It has been the basic starting point in both our previous and current research.…”

mentioning

confidence: 99%

“…As inspired by the designs in [16,28,29], re-investigating the time constant shift on all points of the DCO, design of new current starved (DCV), proper placement of suitable Schmitt triggers, introducing a combined control unit for linearity and balancing the effect of a bit per produced delay of every point of the DCO and a set of new DCO designs are proposed in this paper. The proposed designs are capable of operating in the conventional single-band mode and two newly added modes called dual band and wide band here.…”

mentioning

confidence: 99%

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Two Efficient Dual-Band and Wide-Band Low-Power DCO Designs Using Current Starving Gates, DCV and Reconfigurable Schmitt Triggers in 180 nm

Souri

Ghaznavi‐Ghoushchi

2015

Circuits Syst Signal Process

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Digitally controlled oscillators are the main cores in all-digital phase-locked loops (ADPLL), which are important for determining the range of frequency and power consumption in ADPLLs. In the conventional digitally controlled oscillator (DCO) designs, one single band of operation is assigned to the DCO. The following paper presents a new approach in the design of DCOs, which works in dual-band and wide-band modes with a control unit. In dual-band mode, the DCO works in two different ranges of frequencies simultaneously via digital control bits. The wide-band DCO (WBDCO) works in one wider range of frequencies consecutively. It seems that in the wide-band DCO, the gap width for the dual-band DCO (DBDCO) is zero. The previously mentioned designs allow the designer to have standard frequencies with the help of direct or multiplied frequencies. So, we can have a trade-off between power and performance. This means that we can have low power consumption in low-frequency applications and vice versa. The proposed designs are based on using digitally controlled capacitors, current starving gates and Schmitt triggers in critical points of the DCO loop, while preserving coarse and fine tunings. The non-delay linearity factors are clearly investigated and resolved with the use of a new combined control unit. The simulations of the proposed designs are performed in Hspice with a voltage of VDD = 1.8 v in 180 nm CMOS technology for 64-and 128-bit input coarse codes. Our simulation and evaluation results showed that in the dual-band DCO, a 14.8 ps jitter was calculated at 134 MHz with 1.2131 mW power consumption, while in the wide band with overlap mode, a 68.7 ps jitter was measured at 184.61 MHz

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Section: Schmitt Trigger In Dcomentioning

confidence: 99%

mentioning

confidence: 99%

mentioning

confidence: 99%

“…It gains linearity at the cost of more power. The designs in [16,28,29] are our inspirational start point. It has been the basic starting point in both our previous and current research.…”

mentioning

confidence: 99%

mentioning

confidence: 99%

See 3 more Smart Citations

Two Efficient Dual-Band and Wide-Band Low-Power DCO Designs Using Current Starving Gates, DCV and Reconfigurable Schmitt Triggers in 180 nm

Souri

Ghaznavi‐Ghoushchi

2015

Circuits Syst Signal Process

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A low power varactor based digitally controlled oscillator design in 180 nm CMOS technology

Dabas,

Kumar

2023

SN Appl. Sci.

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This paper reports two distinct architectures for digitally-controlled oscillators (DCOs) utilizing MOS varactor, designed in TSMC 180 nm CMOS technology. The first DCO design employs a CMOS inverter, while the second design features a Three-Transistors (3T) NAND gate as a delay stage inverter. Using these delay stages, three-bit, five-bit, and seven-bit controlled DCO circuits have been designed. For the inverter-based DCO circuit, the frequency spans from 4.844 to 2.708 GHz, 2.523 to 0.853 GHz, and 1.364 to 0.253 GHz, with a power consumption of 0.958 mW, 1.597 mW, and 2.236 mW for three-bit, five-bit, and seven-bit DCO variants, respectively. Further, the 3T-NAND gate-based DCO circuit exhibits oscillation frequencies ranging from 2.024 to 0.517 GHz, 0.867 to 0.131 GHz, and 0.341 to 0.033 GHz, with the resulting power consumption of 0.335 mW, 0.559 mW, and 0.782 mW. Equally significant, the proposed inverter-based DCO attains phase noise of − 102.61 dBc/Hz@1MHz, − 99.65 dBc/Hz@1MHz, and − 117.54 dBc/Hz@1MHz, accompanied by corresponding figures of merit (FoM) 174.94 dBc/Hz, 161.27 dBc/Hz, and 165.10 dBc/Hz for three-bit, five-bit, and seven-bit control words, respectively. For the 3T-NAND gate-based DCO, phase noise levels register at − 93.51 dBc/Hz@1MHz, − 113.07 dBc/Hz@1MHz, and − 106.96 dBc/Hz@1MHz, with FoM values of 160.23 dBc/Hz, 166.70 dBc/Hz, and 150.30 dBc/Hz for three-bit, five-bit, and seven-bit DCO variants, respectively. The comprehensive analysis of the proposed DCOs demonstrates the power supply variations, phase noise deviations, and frequency variations. The reported DCOs perform better with regard to output frequency range, power consumption, and overall FoM.

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A portable high-frequency digitally controlled oscillator (DCO)

Elrabaa

2014

Integration

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A Low-Power Digitally Controlled Oscillator for All Digital Phase-Locked Loops

Cited by 17 publications

References 17 publications

Two Efficient Dual-Band and Wide-Band Low-Power DCO Designs Using Current Starving Gates, DCV and Reconfigurable Schmitt Triggers in 180 nm

Two Efficient Dual-Band and Wide-Band Low-Power DCO Designs Using Current Starving Gates, DCV and Reconfigurable Schmitt Triggers in 180 nm

A low power varactor based digitally controlled oscillator design in 180 nm CMOS technology

A portable high-frequency digitally controlled oscillator (DCO)

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