Sigma-delta noise shaping for digital-to-frequency and digital-to-RF-amplitude conversion

Staszewski, Robert Bogdan; Rezeq, S.; Hung, Chih‐Ming; Cruise, P.; Wallberg, J.

doi:10.1109/iwsoc.2005.97

Cited by 8 publications

(14 citation statements)

References 9 publications

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“…It is based on a digitally controlled power amplifier (DPA) for a low-power all-digital GSM/EDGE transmitter proposed in [2] [6]. The DPA [7], see Figure 4(a), with an efficiency of 17% at 0 dBm output power occupies only 0.005 mm 2 in 90 nm CMOS.…”

Section: A Mismatches In Digital Rf To Amplitude Convertermentioning

confidence: 99%

Digital RF Processing Techniques for Device Mismatch Tolerant Transmitters in Nanometer-Scale CMOS

Waheed

Staszewski

2007

2007 IEEE International Symposium on Circuits and Systems (ISCAS)

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We propose estimation techniques and compensation algorithms against CMOS device variability in an all-digital RF polar transmitter. The transmitter is built using dense and fast digital logic and comprises two converters that transform transmit modulation from digital to RF frequency/phase and amplitude analog domains. The converters built with segmented banks consist of a large number of unit-weighted devices which exhibit a certain level of random and systematic mismatch. The techniques presented are employed in a commercial single-chip GSM/EDGE radio realized in 90 nm CMOS.

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Section: A Mismatches In Digital Rf To Amplitude Convertermentioning

confidence: 99%

Digital RF Processing Techniques for Device Mismatch Tolerant Transmitters in Nanometer-Scale CMOS

Waheed

Staszewski

2007

2007 IEEE International Symposium on Circuits and Systems (ISCAS)

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“…The authors of [2] and [6] have presented high rate digital sigma-delta modulators. However, the presented solutions for these sigma-delta modulators, based on a Digital Phase Accumulator (DPA) in Reference [2] and a pipelining approach in [6], are shown for only low-pass sigma-delta modulators and do not address band-pass sigma-delta structures.…”

Section: The Pipelining Approachmentioning

confidence: 99%

“…This would result in a 2nd order low-pass SDM. Please note that a low-pass SDM can be pipelined as explained in [2] and [6], and is used here just to serve as an example for the proposed approach. The SDM structure is broken into lower significance bits and higher significance bits.…”

Section: The Pipelining Approachmentioning

confidence: 99%

“…By redefining variables in equation 3 and 4, we obtain: Ueven = Xn + I +Xn +tLn (5) Uodt= X,2 + 2) +Un +2 (6) As demonstrated in the above equations, individual loop unrolled structures would produce the even and odd samples of the original structure, while running at half the original frequency. In addition, if the timing constraint for the original structure is TC then the unrolled structure would have more relaxed timing constraints of 2xT,.…”

Section: Loop Unrollingmentioning

confidence: 99%

“…One of the applications of such a digital band-pass SDM is in the Digital RF Processor (DRP)T [4], [5], [6] to enhance the resolution of the transmitter's modulators while controlling the spectrum of their quantization noise [4], [5].…”

Section: Introductionmentioning

confidence: 99%

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Implementation of a High Speed Digital Band-Pass Sigma-Delta Modulator for a Wireless Transmitter

Parikh

Feygin

Balsara

et al.

2005 IEEE Dallas/Cas Workshop on Architecture, Circuits and Implementtation of SOCs

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Digital sigma-delta modulators are used extensively in CMOS wireless SoC designs to achieve high-resolution data conversion while controlling the quantization noise spectrum. This paper presents an implementation of a 90nm CMOS digital band-pass sigma-delta modulator (SDM), running at 900 MHz. Conventional sigma-delta structures required to achieve such noise shaping are hardware intensive and do not meet the timing requirements when synthesized in 90nm technology using a static CMOS implementation. In this work, we present an unrolled LA architecture to achieve the necessary rate of operation. Unrolling is achieved by running two loops at half the frequency, while maintaining algorithmic equivalency between the original and proposed structures. The proposed architecture meets timing requirements of 900 MHz across all PVT corners at the cost of increase in area. The operating frequency for most of the hardware is halved, resulting in a 20% power consumption reduction.

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A Digital Architecture for Direct Digital-to-RF Converters

Heidar-barghi

Gazor

2006

2006 Canadian Conference on Electrical and Computer Engineering

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Sigma-delta noise shaping for digital-to-frequency and digital-to-RF-amplitude conversion

Cited by 8 publications

References 9 publications

Digital RF Processing Techniques for Device Mismatch Tolerant Transmitters in Nanometer-Scale CMOS

Digital RF Processing Techniques for Device Mismatch Tolerant Transmitters in Nanometer-Scale CMOS

Implementation of a High Speed Digital Band-Pass Sigma-Delta Modulator for a Wireless Transmitter

A Digital Architecture for Direct Digital-to-RF Converters

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