A novel architecture for a fully digital wideband wireless transmitter is presented. The proposed structure replaces high-dynamic-range analog circuits with high-speed digital circuits and offers a simple and flexible architecture, which requires less area, consumes less power, and delivers higher performance compared to those of the conventional modulators used for wideband systems. The design is based on a standard 65-nm CMOS process and is suitable for integration with a digital signal processor, memory, and logic implemented in such a process. The presented transmitter is based on a novel digital quadrature modulator (DQM), which achieves digital modulation in a Cartesian coordinate system. The novel architecture employs a single converter, referred to as the differential-like digital-to-RF converter (DDRC), as it is based on fully digitally combining the quadrature baseband signals. The DDRC, at the heart of the DQM, combines functionalities of a mixer, a digital-to-analog converter, and an RF filter into a single circuit. The total area for the digital blocks is 0 04 mm 2 , with a power consumption of roughly 5 mW. It is shown that the proposed transmitter meets the spectral mask, defined in the targeted IEEE 802.16e (WiMAX) standard, with a margin of 20 dB and achieves an error-vector-magnitude (EVM) performance of 36 dB with a margin of 6 dB.Index Terms-Differential-like digital-to-RF converter (DDRC), digital quadrature modulator (DQM), Digital RF Processor (DRP), digital transmitter, software-defined radio (SDR), system-on-chip (SoC), WiMAX.

Digital sigma-delta modulators are used extensively in CMOS wireless SoC designs to achieve high-resolution data conversion while controlling the quantization noise spectrum. This paper presents an implementation of a 90nm CMOS digital band-pass sigma-delta modulator (SDM), running at 900 MHz. Conventional sigma-delta structures required to achieve such noise shaping are hardware intensive and do not meet the timing requirements when synthesized in 90nm technology using a static CMOS implementation. In this work, we present an unrolled LA architecture to achieve the necessary rate of operation. Unrolling is achieved by running two loops at half the frequency, while maintaining algorithmic equivalency between the original and proposed structures. The proposed architecture meets timing requirements of 900 MHz across all PVT corners at the cost of increase in area. The operating frequency for most of the hardware is halved, resulting in a 20% power consumption reduction.

The digital sigma-delta (¦¡) modulators are used extensively in CMOS wireless SoC designs to achieve high-resolution data conversion while controlling the quantization noise spectrum. This paper presents an implementation of a 90nm CMOS digital band-pass ¦¡ modulator, running at 900 MHz. The conventional band-pass ¦¡ structures required to achieve such noise shaping are hardware intensive and do not meet the timing requirements when synthesized in 90nm technology using a static CMOS implementation. The loop-unrolling concept was recently presented as a solution for getting required rate of operation. However, this approach requires larger area and consumes higher power. In this work, we present a new architecture to achieve the necessary noise shaping at required rate of operation. The proposed structure has the different Noise Transfer Function (NTF) compared to conventional band-pass structures and hence it gives more control over the location of zeros. It also meets timing requirements of 900 MHz across all PVT corners and shows significant saving in area and power.

In digitally intensive direct conversion transmitters, the baseband data is up-sampled to the RF rate. As the bandwidth of the baseband data increases, carefully designed cascaded digital filters are required in order to attenuate the wide replicas generated during the digital up-sampling process. Though design methodologies for single stage digital filters are very well established, near-optimum design of such multistage filters typically requires selection of several parameters by trialand-error. This approach is time-consuming and does not assure the optimum solution (i.e. lowest area/power) under various performance constraints. In this paper, a genetic algorithm (GA) based generic automated search methodology for design of such cascaded filters is proposed. The proposed technique is demonstrated for digital WiMAX and WCDMA transmitters, for which near-optimal solutions appear to have been achieved in a relatively short time compared to the traditional manual design techniques.

A fully digital architecture for wideband wireless transmitters is presented, which replaces high dynamicrange analog circuits with high-speed digital circuits and thus offers lower cost and higher performance compared to those of conventional analog transmitters. The proposed transmitter modulates wideband data in Cartesian coordinates and generates its RF output using a fully Digital Quadrature Modulator (DQM). The novel architecture employs a single digital-to-RF converter, as it is based on fully digital combining of the quadrature baseband signals. The design is based on a standard 90nm CMOS process and is suitable for integration with a digital signal processor, memory and logic implemented in such digital process. Although the presented results demonstrate compliance of the transmitter's output with the IEEE 802.16a (WiMAX) standard, the proposed architecture may also be used for many other wideband wireless and non-wireless communication standards.

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This paper presents an energy efficient transmitter for multi-standard applications (IEEE802.15.4, BLE, 5Mbps) in ISM2.4GHz band. It incorporates a fully digital PLL with two point modulation to achieve upto 5Mbps data rate at 9.5mW power consumption (including all power management blocks) at 0dBm output power, leading to 1.9nJ/b efficiency. The proposed digital PLL uses a counter based area and power efficient re-circulating TDC, current reuse low area DCO using resistive tail, process compensated high speed divider, class-AB PA stages, and fully integrated on-chip LDOs. The entire transmitter occupies 0.35mm 2 Silicon area in a 65nm digital CMOS process.Index Terms -multi-standard transmitter, high data rate loop modulator, ultra low energy, digital PLL, low area.