All Digital-Quadrature-Modulator Based Wideband Wireless Transmitters

Parikh, V.K.; Balsara, Poras T.; Eliezer, Oren

doi:10.1109/tcsi.2009.2015600

Cited by 26 publications

(10 citation statements)

References 22 publications

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“…Error vector magnitude (EVM) is another figure of merit used here, which is widely employed in the standards to specify the quality of the transmitted signal [3]. Fig.…”

Section: Simulation Resultsmentioning

confidence: 99%

“…Another circuit imperfection, the delay mismatch (DM), occurs when the signal delays on the I/Q branches are different. It may be the results of different trace lengths, timing skews between the data converters used to generate the analog I/Q signals, and/or group delays of the analog reconstruction lowpass filter (LPF) in the I/Q branches [2], [3].…”

Section: Introductionmentioning

confidence: 99%

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Compensation of Delay Mismatch in a Direct Conversion Transmitter

Zhu

Huang

Leung

2014

IEEE Trans. Circuits Syst. II

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This brief analyzes the effects of the delay mismatch (DM) between in-phase (I) and quadrature (Q) branches of a direct conversion transmitter (DCT) on its image rejection capability. An iterative technique is proposed to compensate for the DM, based on the instantaneous power measurement of the DCT output signal. It is shown that the proposed compensation technique can obtain the true DM value even when the I/Q impairment exists in the DCT. Simulation results show that the proposed technique can effectively compensate for the DM, thereby improving the DCT performance. Index Terms-Correlation function, delay mismatch (DM), direct conversion transmitter (DCT), image rejection, interpolation filter.1549-7747

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“…Error vector magnitude (EVM) is another figure of merit used here, which is widely employed in the standards to specify the quality of the transmitted signal [3]. Fig.…”

Section: Simulation Resultsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Compensation of Delay Mismatch in a Direct Conversion Transmitter

Zhu

Huang

Leung

2014

IEEE Trans. Circuits Syst. II

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“…There has been many different works in recent years that have tried to address the challenges and fulfill the requirements of different wireless communication standards [1][2][3][4][5][6][7][8][9].…”

Section: Introductionmentioning

confidence: 99%

On High-Speed Digital-to-Analog Converters and Semi-Digital FIR Filters

Sadeghifar¹

2015

Linköping Studies in Science and Technology. Thesis

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High-speed and high-resolution digital-to-analog converters (DACs) are vital components in all telecommunication systems. Radio-frequency digital-to-analog converter (RFDAC) provides high-speed and high-resolution conversion from digital domain to an analog signal. RFDACs can be employed in direct-conversion radio transmitter architectures. The idea of RFDAC is to utilize an oscillatorypulse-amplitude modulation instead of the conventional zero-order hold pulse amplitude modulation, which results in DAC output spectrum to have highenergy high-frequency lobe, other than the Nyquist main lobe. The frequency of the oscillatory pulse can be chosen, with respect to the sample frequency, such that the aliasing images of the signal at integer multiples of the sample frequency are landed in the high-energy high-frequency lobes of the DAC frequency response. Therefore the high-frequency images of the signal can be used as the output of the DAC, i.e., no need to the mixing stage for frequency upconversion after the DAC in the radio transmitter. The mixing stage however is not eliminated but it is rather moved into the DAC elements and therefore the local oscillator (LO) signal with high frequency should be delivered to each individual DAC element.In direct-conversion architecture of IQ modulators which utilize the RFDAC technique, however, there is a problem of finite image rejection. The origin of this problem is the different polarity of the spectral response of the oscillatorypulse-amplitude modulation in I and Q branches. The conditions where this problem can be alleviated in IQ modulator employing RFDACs is also discussed in this work.Σ∆ modulators are used preceding the DAC in the transmitter chain to reduce the digital signal's number of bits, still maintain the same resolution. By utilizing the Σ∆ modulator now the total number of DAC elements has decreased and therefore the delivery of the high-frequency LO signal to each DAC element is practical. One of the costs of employing Σ∆ modulator, however, is a higher quantization noise power at the output of the DAC. The quantization noise is ideally spectrally shaped to out-of-band frequencies by the Σ∆ modulator. The shaped noise which usually has comparatively high power must be filtered out to fulfill the radio transmission spectral mask requirement.Semi-digital FIR filter can be used in the context of digital-to-analog conversion, cascaded with Σ∆ modulator to filter the out-of-band noise by the modulator. In the same time it converts the signal from digital domain to an analog quantity. In general case, we can have a multi-bit, semi-digital FIR filter where each tap of the filter is realized with a sub-DAC of M bits. The delay elements are also realized with M-bit shift registers. If the output of the modulator is given by a single bit, the semi-digital FIR filter taps are simply controlled by a single switch assuming a current-steering architecture DAC. One of the major advantages is that the static linearity of the DAC is optimum. Since there are only t...

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“…This architecture is not as amenable to integration as it is analog intensive. Additionally, it is also prone to gain and phase imbalances and to process, voltage, and temperature (PVT) variations [3].…”

Section: Introductionmentioning

confidence: 99%

“…Circuit details and layout methods resulting in very dense CMOS 90nm chip area are explained in Sect. 3. In Sect.…”

Section: Introductionmentioning

confidence: 99%

Direct digital-RF amplitude modulator in CMOS 90nm

Chironi

Debaillie

Basçhirotto

et al. 2011

Analog Integr Circ Sig Process

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Two different wireless transmitter topologies based on an direct digital-RF amplitude modulator (DAM) are presented: a polar modulator and a direct digital-RF IQ modulator prototype. The DAM consists of 255 basic cells digitally activated by an 8-bit amplitude code to shape a non-constant envelope RF output. The cells are segmentaddressed resulting in a very compact 0.007 mm 2 chip area in CMOS 90nm. In order to reduce the spectral images due to the discrete-time to continuous-time conversion a 2-fold interpolation has been implemented. The DAM reaches a peak output power of 5 dBm at 2.45 GHz with 23% drain efficiency. Both direct digital modulator architectures fulfill WLAN 802.11g linearity constrains at 2.45 GHz.

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All Digital-Quadrature-Modulator Based Wideband Wireless Transmitters

Cited by 26 publications

References 22 publications

Compensation of Delay Mismatch in a Direct Conversion Transmitter

Compensation of Delay Mismatch in a Direct Conversion Transmitter

On High-Speed Digital-to-Analog Converters and Semi-Digital FIR Filters

Direct digital-RF amplitude modulator in CMOS 90nm

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