A Low Area and Low Power Digital Band-Pass Sigma-Delta Modulator for Wireless Transmitters

Abstract

The digital sigma-delta (¦¡) modulators are used extensively in CMOS wireless SoC designs to achieve high-resolution data conversion while controlling the quantization noise spectrum. This paper presents an implementation of a 90nm CMOS digital band-pass ¦¡ modulator, running at 900 MHz. The conventional band-pass ¦¡ structures required to achieve such noise shaping are hardware intensive and do not meet the timing requirements when synthesized in 90nm technology using a static CMOS implementation. The loop-unrolling concept was recently presented as a solution for getting required rate of operation. However, this approach requires larger area and consumes higher power. In this work, we present a new architecture to achieve the necessary noise shaping at required rate of operation. The proposed structure has the different Noise Transfer Function (NTF) compared to conventional band-pass structures and hence it gives more control over the location of zeros. It also meets timing requirements of 900 MHz across all PVT corners and shows significant saving in area and power.

All Digital-Quadrature-Modulator Based Wideband Wireless Transmitters

“…The minimum resolution achieved in the DDRC architecture is limited by the smallest transistor available in a given technology and the process mismatch constraint, while the maximum output power delivered is limited by the voltage swing and the area constraint [20], [21]. Therefore, the total resolution offered by the DDRC is fixed, in the range of 9-10 bits for practical implementation, which is not sufficient to generate the WiMAX standard compliant output, and so, it is necessary to increase the resolution of the and signals of Fig.…”

Signal conditioning for polar all-digital OFDM wireless transmitters

“…As the DAC and the mixer are in one block, the reconstruction filter after the DAC is absent. To filter out DAC emissions different techniques like band-pass filtering [5], linear interpolation and sigma-delta architectures [6] have been used. RFDAC-based transmitters use high oversampling and digital filtering to avoid the effect of DAC spurs.…”

“…The phase modulator section of all these polar architectures is implemented either using quadrature up-converters, vector modulators or using PLL and ADPLL circuits [6,12,15]. The use of mixers in phase up-conversion results in mixer spurs and distortion and requires careful filtering design, which increases their foot-print and reduces their ability for integration.…”